OS Task-Aware Caching Controller for Fine-Grained Load Scheduling
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Solution Overview
Problem
Existing information processing systems face inefficiencies in scheduling operations due to the granularity of task processing and interactions between hardware and software, which affects performance and requires a more fine-grained scheduling approach without additional overhead.
Innovation Solution
An operating system task-aware caching (OTC) subsystem with a scheduling structure that includes a load sequence queue, request arbiter, and task information container, allowing for priority-based scheduling and fine-grained observation and anticipation of task state changes, enabling concurrent processing and minimal interaction with non-specialized elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If OS-level task granularity is used for scheduling, then system compatibility is maintained, but scheduling efficiency and performance are limited due to coarse granularity
Solution Approach 1:
The patent segments an OS task into multiple load units (e.g., instruction chunks, data blocks) that can be independently scheduled and processed. This segmentation enables fine-grained scheduling at the load unit level rather than at the coarse OS task level, improving scheduling efficiency and resource utilization while maintaining compatibility with the existing OS task structure.
2Measurement precision
If fine-grained scheduling is implemented, then scheduling precision is improved, but overhead from additional observation and control mechanisms increases
Solution Approach 1:
The patent implements preliminary action by pre-loading load units into a buffer memory before they are actually needed for execution. The scheduling structure anticipates future load requirements and prepares data in advance, reducing the need for frequent observation and control operations during actual execution, thereby lowering overhead while maintaining high scheduling precision.
3Productivity
If load anticipation is performed at OS task level, then system compatibility is maintained, but performance improvement is limited due to coarse granularity
Solution Approach 1:
The patent introduces dynamic granularity control by allowing the scheduling structure to operate at multiple levels: it can schedule individual load units for fine-grained optimization or group them into larger batches when appropriate. This dynamic adaptability enables the system to adjust granularity based on workload characteristics, improving both performance and versatility while maintaining compatibility with OS task structures.
Data Source
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AI summary
A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.