OS Task-Aware Caching Controller for Fine-Grained Load Scheduling
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Solution Overview
Problem
Current information processing systems face inefficiencies in scheduling operations due to the granularity of task processing, which affects performance and requires improved observation and anticipation mechanisms to optimize loading and execution.
Innovation Solution
An apparatus with an operating system task-aware caching (OTC) subsystem that utilizes a load sequence queue, request arbiter, and task information container to perform fine-grained scheduling, generating observation events and anticipation operations for tasks, allowing for concurrent processing and efficient load anticipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional OS task granularity is used for scheduling operations, then system simplicity is maintained, but scheduling efficiency and performance are degraded
Solution Approach 1:
The patent divides OS tasks into smaller load units that can be independently scheduled and processed. This segmentation enables fine-grained scheduling where individual load units within a task can be scheduled separately, improving scheduling efficiency and resource utilization without requiring complete task-level scheduling overhead.
Solution Approach 2:
The patent introduces a new dimension of scheduling by implementing a load sequence queue that tracks and manages load units independently from traditional task scheduling. This adds a finer granularity layer to the scheduling hierarchy, allowing the system to manage both task-level and load-unit-level scheduling simultaneously.
2Measurement precision
If finer granularity observation units are implemented, then observation precision and scheduling accuracy are improved, but system overhead and complexity increase
Solution Approach 1:
The patent segments tasks into load units with configurable sizes, allowing the system to observe and schedule at the load unit level rather than only at the task level. This segmentation provides finer observation precision while keeping the observation mechanism manageable through standardized load unit structures.
Solution Approach 2:
The patent implements dynamic load unit size configuration, where the granularity of observation units can be adjusted based on system requirements. This dynamic adjustment allows the system to optimize between observation precision and overhead by adapting the load unit size to match the specific scheduling and observation needs.
3Speed
If load anticipation operations are performed, then system performance and responsiveness are improved, but processing overhead and energy consumption increase
Solution Approach 1:
The patent implements load anticipation by pre-loading load units into the load sequence queue before they are actually needed for execution. This preliminary action allows the system to prepare data in advance, reducing wait times and improving responsiveness while enabling batch processing that can optimize energy consumption.
Solution Approach 2:
The patent implements selective load anticipation where only certain load units are pre-loaded based on priority and system state, rather than anticipating all loads. This partial action approach balances the benefit of improved responsiveness against the cost of processing overhead and energy consumption by being selective about which loads to anticipate.
Data Source
AI summary
A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.