Semiconductor Device Using OS Transistors for Dynamic Logic
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing the number of transistors, increasing operating speed, reducing power consumption, and achieving high rewrite endurance.
Innovation Solution
A semiconductor device is designed with a memory cell that includes three transistors of a single conductivity type and a capacitor, along with a dynamic logic circuit that utilizes OS transistors to minimize leakage current and reduce the number of transistors required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor devices use multiple transistor types and complex circuit configurations, then reliability may be improved, but device complexity and number of transistors increase
Solution Approach 1:
The patent employs transistors of a single conductivity type (all n-channel or all p-channel) throughout the memory cell and logic circuit, eliminating the need for complementary transistor pairs. This homogeneous approach reduces transistor count while maintaining reliable operation through unified device characteristics and simplified circuit design.
Solution Approach 2:
The memory cell transistors serve multiple functions: data storage, read operation, write operation, and circuit selection. By designing transistors that can perform multiple operations within a single cell, the patent reduces the total number of transistors needed compared to conventional designs that require separate dedicated transistors for each function.
2Stability of the object's composition
If conventional logic circuits use static logic designs, then stability is improved, but power consumption increases due to continuous current flow
Solution Approach 1:
The patent implements dynamic logic circuits that operate in periodic cycles: precharge phase where capacitors are charged to a reference voltage, and evaluate phase where logic operations occur. This periodic operation allows the circuit to remain stable during precharge while consuming minimal power during evaluation, unlike static logic that continuously consumes power.
Solution Approach 2:
The dynamic logic circuit discards accumulated charge from capacitors during the precharge phase and recovers it during evaluation. This cyclical charging and discharging of capacitive elements enables the circuit to reset to a stable state periodically while consuming power only during active evaluation, reducing overall power consumption compared to continuously biased static logic.
3Speed
If dynamic logic circuits are used to reduce power consumption, then operating speed may improve, but leakage current becomes more problematic
Solution Approach 1:
The patent employs metal oxide semiconductor transistors (MOS) with specific material properties that provide extremely low off-state leakage current. This material choice enables dynamic logic operation at lower frequencies where leakage is minimal, while still achieving high operating speeds during active phases. The composite structure of metal oxide channels provides both low leakage and high on-state current capability.
Solution Approach 2:
The circuit performs preliminary precharging of capacitive nodes to a defined reference voltage before logic evaluation begins. This preliminary action establishes a stable starting state that minimizes the impact of leakage current during the subsequent evaluation phase, ensuring that leakage does not significantly affect the logic operation outcome even at higher operating speeds.
4Ease of manufacture
If the number of transistors is reduced to simplify device structure, then manufacturing ease improves, but operating speed may decrease due to fewer parallel operations
Solution Approach 1:
The patent merges multiple functions into single transistors and shared circuit elements. For example, the same transistor serves as both a storage element and a read/write switch, and bit lines are shared between multiple memory cells. This merging reduces the total transistor count for easier manufacturing while maintaining high operating speed through efficient resource utilization and reduced signal path lengths.
Data Source
AI summary
A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.