OS Transistor Memory Layout With Fewer Interlayer Connections
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving low power consumption, high reliability, layout flexibility, miniaturization, and integration, particularly due to limitations in transistor off-state current and impurity diffusion issues.
Innovation Solution
A semiconductor device design incorporating a cell array with OS transistors, where the transistors have a metal oxide channel formation region, including a back gate structure and specific metal elements like aluminum, ruthenium, or tungsten, to reduce off-state current and enhance reliability, allowing for single-polarity circuit formation and reduced connection points for improved flexibility and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional transistors are used in memory cells, then the device can be manufactured with standard processes, but the off-state current is too high leading to high power consumption
Solution Approach 1:
The patent changes the material parameter of the transistor channel from conventional silicon to oxide semiconductor, which fundamentally alters the electrical characteristics to achieve extremely low off-state current (10^-21 to 10^-24 A) while maintaining good data retention properties
Solution Approach 2:
The patent employs composite material structures including oxide semiconductor layers combined with specific metal elements (Al, Ru, W) and insulating layers to create transistors that simultaneously achieve low off-state current and high reliability for data retention
2Adaptability or versatility
If multiple transistor types are used in the semiconductor device, then specific functions can be optimized, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent makes all transistors in the semiconductor device use the same oxide semiconductor material and structure, enabling a single transistor design to fulfill multiple functions (memory cell transistors, driver circuit transistors, control circuit transistors) thereby reducing device complexity while maintaining versatility
Solution Approach 2:
The patent divides the semiconductor device into functional segments (memory cell array, first driver circuit, second driver circuit, control circuit) where each segment uses the same oxide semiconductor transistor technology, allowing modular design and simplified manufacturing
3Ease of operation
If transistors with different polarities are used, then circuit design flexibility is improved, but the number of connection points and manufacturing steps increase
Solution Approach 1:
The patent uses uniform oxide semiconductor transistors with the same polarity throughout the entire device, creating homogeneous transistor characteristics that simplify circuit design and reduce the number of connection points while maintaining layout flexibility through consistent device behavior
4Productivity
If the semiconductor device is miniaturized, then integration density is improved, but impurity diffusion and manufacturing precision become more difficult to control
Solution Approach 1:
The patent employs oxide semiconductor materials that inherently resist impurity diffusion and provide stable electrical characteristics even in miniaturized structures, effectively creating an inert environment that protects against manufacturing variability and enables high integration density with controlled impurity levels
Data Source
AI summary
A novel semiconductor device formed with single-polarity circuits using OS transistors is provided. Thus, connection between different layers in a memory circuit is unnecessary. This can reduce the number of connection portions and improve the flexibility of circuit layout and the reliability of the OS transistors. In particular, many memory cells are provided; thus, the memory cells are formed with single-polarity circuits, whereby the number of connection portions can be significantly reduced. Further, by providing a driver circuit in the same layer as the cell array, many wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, and the number of connection portions can be further reduced. An interposer provided with a plurality of integrated circuits can function as one electronic component.