OS-Transparent Memory Decompression Hardware Acceleration
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Solution Overview
Problem
Current memory compression solutions, such as ZSWAP and ZRAM, incur significant overhead due to page faults and operating system involvement when accessing compressed data, limiting the size of the compressed memory partition and reducing performance.
Innovation Solution
An OS-transparent memory decompression scheme that uses hardware acceleration to decompress read requests from compressed memory without generating page faults, by defining a new compressed physical address space and utilizing on-chip caching to store decompressed data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If current memory compression solutions (ZSWAP, ZRAM) are used, then memory compression is achieved, but page fault overhead increases access latency
Solution Approach 1:
The patent extracts the page fault handling overhead from the memory access path by implementing OS-transparent hardware decompression. The hardware decompression engine directly decompresses data in the memory controller without involving the OS page fault mechanism, thereby removing the time-consuming OS intervention from the critical access path while maintaining the compressed memory capacity benefits.
Solution Approach 2:
The patent introduces a hardware decompression engine as an intermediary component between the compressed memory and the processor. This intermediary handles decompression transparently in hardware, acting as a bridge that eliminates the need for OS page fault handling while maintaining the compressed memory structure. The decompression engine processes data requests directly without requiring OS involvement, thus reducing access latency.
2Productivity
If OS page fault handling is used for decompression, then decompression can be performed, but OS overhead reduces performance
Solution Approach 1:
The patent implements self-service decompression where the hardware decompression engine autonomously handles all decompression operations without OS intervention. The memory controller's decompression engine automatically decompresses data when needed, managing the entire decompression process independently. This eliminates OS overhead completely while maintaining high decompression throughput through dedicated hardware acceleration.
Solution Approach 2:
The patent replaces the software-based OS page fault handling mechanism with a hardware-based decompression engine. The mechanical/software system of OS interrupts, context switches, and software decompression is substituted with a dedicated hardware decompression engine that operates in parallel, eliminating OS overhead and significantly improving decompression throughput through hardware acceleration.
3Quantity of substance
If compressed memory partition size is increased, then more data can be compressed, but access latency increases due to more page faults
Solution Approach 1:
The patent extracts the page fault overhead from the access path, enabling the compressed memory partition to be scaled up without proportionally increasing access latency. By removing the OS page fault mechanism from the critical path, the system can accommodate larger compressed memory partitions while maintaining consistent low-latency access performance through direct hardware decompression.
4Productivity
If hardware accelerators are used, then decompression speed increases, but parallelism is limited by page fault handling
Solution Approach 1:
The patent enables continuous decompression operations by eliminating the discontinuous page fault interruptions. The hardware decompression engine maintains continuous operation, processing decompression requests in a streamlined pipeline without OS context switches or interrupt handling. This continuity maximizes the utilization of hardware accelerator bandwidth and enables higher parallelism across multiple decompression operations.
Data Source
AI summary
Methods and apparatus for Operating System (OS)-transparent memory decompression with hardware acceleration. A physical address space for system memory is partitioned into compressed and uncompressed partitions. A core issues a memory Read request and on-chip L1, L2, and a last level cache (LLC) are checked, with misses leading to page table lookups to determine where in system memory the requested data are stored. When stored in the compressed partition, a compressed page table is searched to find the location of the compressed form of the data on a memory device. The compressed data are read from the memory device, decompressed using hardware acceleration and returned to the requesting core without writing the data to the uncompressed partition. Under one approach, a compressed page containing the requested data is decompressed and written to the LLC. When data (e.g., cache lines) in the decompressed page in the LLC are written to, the decompressed page is evicted from the LLC and written to the uncompressed partition.