Oscillating Clock Circuit for Phase Skew Correction
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Solution Overview
Problem
In semiconductor apparatuses, phase skew among internal clock signals generated from a system clock signal leads to a reduced valid window for signal synchronization due to varying delay amounts in clock paths, which existing technologies fail to effectively correct.
Innovation Solution
An oscillating signal generating circuit comprising a first clock delaying circuit, a timing control circuit, and an oscillating driver, which delays and controls the oscillating signal to generate control signals to drive the signal to specific logic levels, effectively compensating for delay skew by synchronizing the rising and falling edges of the oscillating signal with the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple clock paths are used to generate internal clock signals, then frequency division and multiplication can be achieved, but phase skew occurs due to different delay amounts
Solution Approach 1:
The patent implements a feedback mechanism where the generated oscillating signal is fed back to the clock delaying circuit to automatically adjust and equalize the delay amounts of multiple clock paths. This closed-loop feedback system continuously monitors and corrects phase skew, ensuring all clock paths have equal delay without requiring manual calibration.
Solution Approach 2:
The system employs self-service through automatic delay equalization where the clock delaying circuit autonomously adjusts its own delay characteristics based on the feedback from the oscillating signal. This eliminates the need for external intervention or complex calibration procedures, allowing the system to self-correct phase skew automatically.
2Manufacturing precision
If delay equalization is implemented to correct phase skew, then synchronization is improved, but circuit complexity increases
Solution Approach 1:
The patent merges the delay equalization function with the existing clock distribution structure by integrating the feedback mechanism directly into the clock delaying circuit. This combination approach avoids adding separate complex equalization circuits, thereby correcting phase skew while minimizing increases in overall circuit complexity.
Solution Approach 2:
The clock delaying circuit is designed with multi-functionality, serving both as a delay element for frequency division/multiplication and as an automatic delay equalization device through the feedback mechanism. This universal design eliminates the need for dedicated equalization circuits, reducing overall system complexity while achieving precise phase skew correction.
3Device complexity
If fixed delay circuits are used, then timing control is simplified, but process variation and degradation cause delay inaccuracies
Solution Approach 1:
The patent transitions from static fixed delay circuits to dynamic delay adjustment through the feedback mechanism. The delay amount is no longer fixed but dynamically adapts based on the oscillating signal feedback, allowing the circuit to compensate for process variation and degradation automatically, thereby maintaining delay accuracy under varying conditions.
Solution Approach 2:
The system implements parameter changes by allowing the delay amount to vary dynamically rather than remaining fixed. The feedback mechanism continuously adjusts the delay parameter based on the oscillating signal characteristics, enabling the circuit to adapt to process variation and degradation while maintaining accurate timing control.
Data Source
AI summary
An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.