Conductive Pads With Oscillating Traces For Low Impedance Interconnects
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Solution Overview
Problem
Existing methods for forming conductive pads in microelectronic devices, such as rastering and photolithography, result in uneven surfaces and inefficiencies, particularly for small production quantities, and fail to meet the demand for compact, high-density interconnects with low impedance in portable devices and data servers.
Innovation Solution
A conductive pad is formed on a dielectric region with a conductive element extending in an oscillating or spiral path, where a theoretical straight line intersects at least three segments, and an electrically conductive bonding material with a melting temperature below 300°C is used to bridge the gaps between adjacent segments, allowing for efficient electrical interconnection with a second component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If rastering is used to form conductive pads, then conductive pads can be formed on dielectric elements, but the pads have uneven surfaces due to overlapping segments
Solution Approach 1:
The conductive pad is divided into multiple discrete segments rather than being formed by continuous rastering. These segments are separated by spaces and do not overlap, eliminating the surface uniformity problems caused by rastering while still providing continuous electrical connectivity through the bonding material that fills the spaces between segments.
2Manufacturing precision
If photolithography is used to form conductive pads, then pads can be formed with precise patterns, but the process is inefficient and burdensome for small production quantities
Solution Approach 1:
The conductive segments are pre-formed on the dielectric element before final assembly. This preliminary formation of conductive structures eliminates the need for time-consuming mask design, testing, and correction processes associated with photolithography, while still achieving precise patterns through controlled segment placement.
3Area of stationary object
If chips are packed densely to reduce device size, then portable devices become more compact, but interconnection complexity and impedance increase
Solution Approach 1:
The conductive segments are arranged in specific geometric patterns (such as interdigitated or alternating patterns) that optimize electrical connectivity in the planar dimension. This dimensional arrangement reduces impedance and simplifies interconnection complexity while maintaining compact device footprint by efficiently utilizing the available surface area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of compact, high-density interconnects with low impedance, improving the bandwidth and reducing power consumption in complex devices by providing short, efficient electrical paths without increasing the assembly size.
Implementation Method 1
an electrically conductive bonding material having a melting temperature below 300° C. joined to the conductive pad and bridging the exposed portion of the surface between the at least two adjacent segments
Data Source
AI summary
An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself.