Oscillation Circuit With Variable Pulse Period for Output Voltage Stability
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Solution Overview
Problem
Existing power supply devices struggle to effectively suppress changes in output voltage due to limitations in on-duty of the PWM signal, leading to potential fluctuations when input voltage varies.
Innovation Solution
The power supply device incorporates an oscillation circuit that variably controls the pulse period of the clock signal based on the PWM signal, using a pulse period control circuit to adjust the duty information signals and generate a ramp voltage, thereby extending the pulse period to maintain output voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the pulse period of the clock signal is extended to suppress output voltage changes, then the output voltage stability is improved, but the response speed to input voltage variations deteriorates
Solution Approach 1:
The oscillation circuit dynamically adjusts the pulse period of the clock signal based on the duty ratio of the PWM signal. When the duty ratio approaches saturation (0% or 100%), the circuit automatically extends the pulse period to prevent further duty ratio adjustment, thereby maintaining output voltage stability while allowing fast response when there is still adjustment margin.
Solution Approach 2:
The circuit changes the time parameter (pulse period) of the clock signal based on the operating conditions. By varying the pulse period according to the PWM duty ratio status, the circuit optimizes both the response speed and output voltage stability under different input voltage conditions.
2Stability of the object's composition
If the PWM duty ratio is increased to compensate for input voltage drops, then the output voltage stability is improved, but the device reaches duty saturation and cannot further suppress voltage changes
Solution Approach 1:
The circuit introduces a new dimension of control by adding pulse period adjustment to the traditional duty ratio control. When the duty ratio reaches saturation, the system transitions to controlling the pulse period, effectively adding a second control dimension to maintain output voltage stability beyond the limits of duty ratio adjustment alone.
Solution Approach 2:
The oscillation circuit acts as an intermediary between the PWM signal and the clock signal generation. It monitors the PWM duty ratio and intervenes by adjusting the clock signal pulse period when the duty ratio approaches saturation, preventing the loss of voltage control capability.
3Device complexity
If the oscillation circuit uses a fixed pulse period, then the circuit simplicity is maintained, but the ability to suppress output voltage changes under varying input conditions is limited
Solution Approach 1:
The oscillation circuit transitions from a fixed pulse period design to a dynamic pulse period design that automatically adjusts based on PWM duty ratio feedback. This dynamic adjustment capability significantly improves output voltage stability under varying input conditions while adding minimal circuit complexity through the use of existing PWM signal monitoring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses output voltage changes by extending the pulse period of the PWM signal, ensuring stable output voltage even with varying input voltage conditions.
Implementation Method 1
a comparator configured to generate a pulse-driven clock signal according to a ramp voltage and a reference voltage
Implementation Method 2
a ramp voltage generation circuit configured to generate a ramp voltage on the basis of a reference voltage
Data Source
AI summary
Provided is an oscillation circuit including a ramp voltage generation circuit generating a ramp voltage according to a first reference voltage, and a comparator generating a pulse-driven clock signal according to the first reference voltage and the ramp voltage. The ramp voltage generation circuit includes a first signal generation circuit generating a first signal that rises or falls according to a duty ratio of a first pulse width modulation signal generated according to a pulse period of the clock signal, and a second signal generation circuit generating a second signal that rises or falls in a direction opposite to the first signal according to the duty ratio of the first pulse width modulation signal. The ramp voltage generation circuit generates the ramp voltage according to the lowest voltage among a second reference voltage based on the first reference voltage, the first signal, and the second signal.