Gated Oscillation Circuit Stabilization Control
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Solution Overview
Problem
Gated oscillation circuits in semiconductor devices face challenges in rapidly and stably terminating oscillation operations when the oscillation enable signal is deactivated, leading to undefined intermediate signal levels and potential malfunctions in internal circuits due to unstable voltage transitions.
Innovation Solution
The oscillation circuit includes a control unit that activates and deactivates a control signal based on detection signals from inverters, ensuring that the oscillation operation is stopped only after the voltage levels are stabilized, using a delay unit, transmission unit, and latch unit to manage signal transmission and phase differences between nodes, and a reset signal generator to confirm stabilization before deactivating the control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the switch is turned OFF immediately when the oscillation enable signal is deactivated, then the oscillation circuit stops the oscillation operation quickly, but the periodic signal at the node becomes unstable and remains in an undefined intermediate level for a considerable period
Solution Approach 1:
The patent applies preliminary action by detecting the voltage level of the periodic signal before turning off the switch. The control unit monitors whether the signal has reached a stable state (logical high or low) and only then deactivates the switch. This prevents the signal from being cut off during an unstable transition period, thereby maintaining signal reliability while still achieving rapid termination of oscillation operations.
2Reliability
If the switch is kept ON to maintain signal stability, then the periodic signal remains stable at the node, but the oscillation operation continues for a considerable period after the oscillation enable signal is deactivated
Solution Approach 1:
The patent implements feedback by continuously monitoring the voltage level of the periodic signal at the node and using this information to control the switch state. The control unit receives feedback about the signal stability and adjusts the switch accordingly - keeping it ON when the signal is unstable and turning it OFF when the signal reaches a stable logical state. This feedback mechanism ensures signal reliability while minimizing unnecessary continuation of oscillation operations, thus reducing time loss.
3Speed
If the switch is turned OFF during signal transition, then the oscillation operation stops rapidly, but internal circuits operating in response to the periodic signal may malfunction due to undefined signal levels
Solution Approach 1:
The patent applies preliminary action by checking the voltage level of the periodic signal before turning off the switch. The control unit monitors whether the signal has reached a stable state (logical high or low) and only then deactivates the switch. This prevents the signal from being cut off during an unstable transition period, thereby maintaining signal reliability while still achieving rapid termination of oscillation operations.
Solution Approach 2:
The patent implements feedback by continuously monitoring the voltage level of the periodic signal at the node and using this information to control the switch state. The control unit receives feedback about the signal stability and adjusts the switch accordingly - keeping it ON when the signal is unstable and turning it OFF when the signal reaches a stable logical state. This feedback mechanism ensures signal reliability while minimizing unnecessary continuation of oscillation operations, thus reducing time loss.
Data Source
AI summary
An oscillation circuit, and a semiconductor device incorporating same, include: an oscillation unit with a plurality of inverters and configured to perform signal transmission between first and second nodes of the inverters such that each of the inverters performs an oscillation operation to generate clock signals having different phases when a control signal is activated, and latch a clock signal of the second node and cut off the signal transmission between the first and second nodes to stop the oscillation operations of the inverters when the control signal is deactivated; and a control unit to activate the control signal when an oscillation enable signal is activated, and deactivate the control signal using one of a clock signal output from an inverter connected to the second node and clock signals of which the phases lag that of a clock signal of the first node, when the oscillation enable signal is deactivated.


