Oscillation Reduction Unit for CAN Bus Systems
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Solution Overview
Problem
In bus systems, particularly in CAN and CAN FD systems, there is a tendency for oscillation during transitions between bit states, leading to increased bit times and reduced transmission rates due to insufficient damping, which can result in transceivers mistakenly recognizing dominant states as recessive, and this limits design flexibility and increases emission in critical frequency ranges.
Innovation Solution
An oscillation reduction unit comprising two back-to-back transistors connected between bus cores, with a timing control block that switches the transistors on during dominant-to-recessive state changes and off during recessive states, reducing oscillation duration and enhancing bit rate and noise immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bit time is extended to sufficiently dampen oscillation during transition from dominant to recessive state, then oscillation is reduced and transmission reliability is improved, but transmission rate decreases
Solution Approach 1:
The oscillation reduction circuit is activated before the bit transition occurs (during the dominant state) and switched off after the transition to recessive state. This preliminary action dampens the oscillation that would otherwise occur during the transition, allowing for shorter bit times without compromising signal integrity or transmission reliability.
2Device complexity
If conventional transceiver design is used without oscillation reduction circuit, then device complexity is low, but oscillation during state transition causes errors and limits transmission speed
Solution Approach 1:
An oscillation reduction circuit is introduced as an intermediary component between the transceiver output and the bus. This circuit actively compensates for oscillation effects during state transitions, enabling higher transmission speeds without causing bit errors, thus resolving the trade-off between simplicity and performance.
3Ease of manufacture
If standard bus topology with termination resistors is used, then system design is simple, but oscillation during bit transitions increases and requires longer bit times
Solution Approach 1:
The oscillation reduction circuit applies a counteracting signal in advance during the dominant state to prevent oscillation from occurring during the transition to recessive state. This preliminary anti-action neutralizes the oscillatory tendency before it can affect signal integrity, allowing for shorter bit times while maintaining standard bus topology designs.
Data Source
Figure 1
Figure 2
Figure 3A~5B
AI summary
The invention relates to an oscillation reduction unit (15; 150; 1500) for a bus system (1) and to a method for reducing an oscillation inclination when transitioning between different bit states. The oscillation reduction unit (15; 150; 1500) has two transistors (151, 152) which are arranged anti-serially between a first bus wire (41) of a bus (40) of the bus system (1) and a second bus wire (41) of the bus (40), wherein an exclusive collision-free access of a participant station (10, 20, 30) to the bus (40) of the bus system (1) is at least temporarily ensured in the bus system (1), and a time control block (142) for switching the two transistors (151, 152). The time control block (142) is designed to switch on the two transistors (151, 152) while a signal (CAN_H, CAN_L) on the first and/or second bus wire (41, 42) and/or a transmission signal (TxD), from which the signals on the first and/or second bus wire (41, 42) are generated, changes from a dominant state (402) to a recessive state (41), and the time control block (142) is also designed to switch off the two transistors (151, 152) if the signal (CAN_H, CAN_L) on the first and/or second bus wire (41, 42) and/or the transmission signal (TxD) is/are switched to the recessive state (401).