Crystal Oscillator Amplitude Regulator With Back-Bias Threshold Control

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Solution Overview

Problem

Existing amplitude regulators in oscillator circuits, particularly in Pierce oscillators, lack precise control over when to switch off to optimize power efficiency and phase noise, limiting their performance.

Innovation Solution

An amplitude regulator circuit utilizing PMOS and NMOS transistors with a back-bias circuit to adjust the threshold voltage of the second NMOS transistor, allowing precise control over when to turn off the amplitude regulation, thereby improving power efficiency and phase noise performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the amplitude regulator is switched off early to improve power efficiency, then power consumption is reduced, but the phase noise performance deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidphase noise
Core Design Contradiction:
Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the threshold voltage of the second NMOS transistor through back-bias control. By varying the back-bias voltage applied to the back-gate terminal of the second NMOS transistor, the threshold voltage is modulated to achieve precise control over the switching point of the amplitude regulator. This enables optimization of both power consumption and phase noise performance by finding the optimal threshold voltage parameter that balances early switching-off (for power efficiency) with adequate signal amplitude (for phase noise performance)

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If the amplitude regulator switches off at a higher voltage threshold, then power efficiency improves, but the tuning precision and control accuracy deteriorate

Engineering Contradiction:
Improvepower efficiencyVSAvoidswitching point control accuracy
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent implements dynamics by making the threshold voltage of the second NMOS transistor dynamically adjustable through back-bias control. Instead of a fixed threshold voltage, the back-bias circuit allows real-time modulation of the threshold voltage parameter. This dynamic control mechanism enables precise adjustment of the switching point voltage threshold, achieving both high power efficiency (through higher thresholds) and high tuning precision (through fine-grained voltage control via back-bias adjustment)

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables sharper tuning of the amplitude regulation, reducing power consumption and phase noise by accurately controlling the amplitude regulator's switching point, enhancing the overall performance of oscillator circuits.

Implementation Method 1

a back-bias circuit portion arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor, thereby varying a threshold voltage of said second NMOS transistor

Methodology Applied
Scientific EffectBack-bias effect:

Implementation Method 2

crystal oscillator circuits, which use a piezoelectric crystal (e.g. a quartz crystal) as the filter

Methodology Applied
Scientific EffectPiezoelectric effect: Piezoelectric Effect

Data Source

PatentUS12184233B2Amplitude regulator for crystal oscillator
Publication Date: 2024.12.31 NORDIC SEMICONDUCTOR
  • US12184233B2 patent drawing
  • US12184233B2 patent drawing
  • US12184233B2 patent drawing

AI summary

An amplitude regulator circuit portion is arranged to supply a current to an inverter in an oscillator circuit. The regulator monitors a voltage at the input terminal of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises first, second, and third PMOS transistors, and first and second NMOS transistors and is arranged such that an input node is connected to the input terminal of the inverter, a respective gate terminal of each of the first and second NMOS transistors, and a respective drain terminal of the first NMOS and first PMOS transistors. The amplitude regulator also comprises a back-bias circuit portions arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor, to vary a threshold voltage, where the threshold voltage of the second NMOS transistor is lower than that of the first NMOS transistor.