Crystal Oscillator Bias Reset for Lower Reference Clock Phase Noise
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Solution Overview
Problem
Existing crystal oscillators face challenges in reducing phase noise of the reference clock without introducing side effects, as existing methods often require additional circuits and complex calibration procedures.
Innovation Solution
A phase noise reduction method that utilizes a reset signal to reset the bias voltage of the crystal oscillator, providing an AC ground path for resistor noise without calibrating the timing of the reset operation, thereby reducing phase noise without significant side effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuits are added to reduce phase noise, then phase noise performance is improved, but device complexity increases
Solution Approach 1:
The patent extracts the noise-generating component (resistor) from the bias circuit and replaces it with a noiseless current source. This removes the harmful element (resistor noise) while maintaining the necessary biasing function, thereby improving phase noise performance without adding circuit complexity.
Solution Approach 2:
The patent employs automatic gain control and amplitude stabilization circuits that self-regulate the oscillation amplitude without external intervention. These circuits automatically adjust to maintain constant amplitude, eliminating the need for manual calibration or additional control mechanisms, thus improving performance without increasing complexity.
2Reliability
If calibration procedures are implemented to reduce phase noise, then phase noise performance is improved, but ease of operation deteriorates
Solution Approach 1:
The patent implements automatic amplitude stabilization and gain control circuits that continuously monitor and adjust the oscillation amplitude without user intervention. The system self-calibrates by detecting amplitude variations and automatically adjusting bias conditions, eliminating manual calibration procedures while maintaining optimal phase noise performance.
Solution Approach 2:
The patent incorporates feedback mechanisms where the output amplitude is detected and fed back to control the biasing conditions. This closed-loop feedback automatically maintains constant amplitude by adjusting the current source bias, eliminating the need for manual calibration and simplifying operation while improving phase noise characteristics.
3Reliability
If bias voltage is stabilized to reduce phase noise, then phase noise performance is improved, but use of energy increases
Solution Approach 1:
The patent removes the resistive biasing element that consumes power and generates noise, replacing it with a high-impedance current source. This extraction of the harmful resistor eliminates both the noise source and the associated power dissipation, achieving phase noise reduction without significant energy penalty.
Solution Approach 2:
The patent changes the biasing parameter from voltage (through resistors) to current (through current sources). This parameter transformation allows for high-impedance biasing that minimizes power consumption while maintaining stable operating conditions and reducing phase noise, as current sources can provide stable bias with lower power dissipation.
Data Source
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AI summary
A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.