Oscillator Clock Calibration by Transition Counting Under Aliased Sampling

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Solution Overview

Problem

Existing oscillator calibration techniques face challenges in achieving accuracy, simplicity, and low overhead, particularly in low power consumption devices and environments where PVT variations cause synchronization issues.

Innovation Solution

A novel calibration method using sampling theory, where the oscillator frequency is sampled at a reference clock frequency, and the samples are compared to a threshold to count transitions, allowing for the determination and correction of the oscillator frequency to compensate for PVT variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If PLL-based calibration techniques are used, then frequency accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvefrequency accuracyVSAvoidcalibration circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts only the essential calibration function from complex PLL circuits by using a simple counter to count oscillator cycles during a predetermined time period. This removes unnecessary PLL components while retaining the core frequency calibration capability, directly resolving the contradiction between accuracy and complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces expensive, complex PLL calibration circuits with a simple, low-cost counter-based approach. The counter is a minimalistic component that provides sufficient calibration accuracy without the overhead of PLL circuitry, effectively using a 'cheap' solution to replace a 'expensive' one.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Device complexity

If integer counting based calibration is used, then device complexity is reduced, but measurement precision deteriorates

Engineering Contradiction:
Improvecalibration circuit complexityVSAvoidfrequency calibration accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by establishing a predetermined time period for counting oscillator cycles. This fixed time window is set in advance to ensure consistent and accurate frequency measurements, improving precision without adding circuit complexity. The predetermined period acts as a preparatory measure that guarantees measurement accuracy.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If manual calibration is used, then device complexity is reduced, but productivity deteriorates

Engineering Contradiction:
Improvecalibration circuit complexityVSAvoidcalibration speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements self-service by enabling the system to automatically perform frequency calibration without human intervention. The microcontroller automatically counts oscillator cycles, compares the count to a reference value, and adjusts the oscillator frequency accordingly. This automated self-calibration process dramatically improves productivity while maintaining low device complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4564682A1Sampling-based clock calibration technique
Publication Date: 2025.06.04 INSTITUT MINES TELECOM TELECOM BRETAGNE
  • EP4564682A1 patent drawingFigure 1~2(d)
  • EP4564682A1 patent drawingFigure 3~4(c)
  • EP4564682A1 patent drawingFigure 5(a)~6(d)

AI summary

Method for calibrating an oscillator frequency fosc of an oscillator signal in an electronic system functioning at a reference clock with a frequency fclock, comprising: a) sampling of fosc at fclock; b) comparing the samples to a threshold value and obtaining a binary comparison signal; c) counting the number of transitions from zero to one and/or from one to zero in the comparison signal during a number of cycles Ntrans-calib of the reference clock; d) in case fclock ≥ 2 fosc-id where fosc-id is the ideal oscillator frequency, determining the real oscillator frequency: fosc−real=fosc−idNtrans−realNtrans−id Ntrans-real is the counted number of transitions and Ntrans-id is the ideal number of transitions that should occur during Ntrans-calib; in case fclock < 2 * fosc-id, determining the real perceived oscillator frequency fperceived−real=fperceived−idNtrans−realNtrans−id fperceived-id is the ideal perceived oscillator frequency fperceived−id=fosc−id−fclock⋅fosc−idfclock the represents the rounding function; e) correcting the oscillator frequency until Ntrans-real = Ntrans-id