Oscillator Clock Correction Circuit Without PLL Complexity
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Solution Overview
Problem
Existing chip designs face challenges in correcting frequency errors in clock signals generated by oscillators, particularly in image sensor chips, which can lead to operational failures or errors in image sensing results.
Innovation Solution
A chip with automatic clock signal correction, comprising a transmission interface, an oscillator, and a correction logic circuit, which counts discontinuous first and second clock signals to calculate a correction value and adjust the frequency of the second clock signal accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the oscillator in the image sensor chip generates a clock signal, then the chip can perform operations, but frequency errors in the clock signal cause operational failures or image sensing errors
Solution Approach 1:
The patent implements a feedback mechanism where the correction logic circuit continuously monitors the frequency of the clock signal generated by the oscillator and automatically adjusts it. The circuit counts clock cycles, detects frequency deviations, and generates correction values that are fed back to the oscillator to maintain accurate frequency, thereby resolving the contradiction between operational reliability and frequency precision.
Solution Approach 2:
The correction logic circuit is designed to automatically detect and correct frequency errors without external intervention. The system performs self-diagnosis by counting clock cycles and comparing them against expected values, then self-corrects by adjusting the oscillator frequency, enabling the chip to maintain reliable operation with high frequency precision autonomously.
2Measurement precision
If the conventional solution adopts the oscillator of the Phase Locked Loop (PLL) circuit to generate a clock signal with a minor frequency error, then the frequency precision is improved, but the complexity of chip design, manufacturing cost and chip size are all increased
Solution Approach 1:
The patent extracts only the essential frequency correction functionality from the complex PLL circuit, implementing a simplified correction logic circuit that performs the critical function of frequency adjustment without the full PLL architecture. This approach achieves the necessary frequency precision while significantly reducing chip design complexity and manufacturing cost.
Solution Approach 2:
The correction logic circuit dynamically adjusts the frequency parameter of the clock signal by counting clock cycles and generating correction values based on detected deviations. This parameter-based correction approach achieves frequency precision comparable to PLL circuits but with simpler design and lower complexity.
Data Source
AI summary
Disclosed are a chip with automatic clock signal correction and an automatic correction method. The chip includes a transmission interface, an oscillator and a correction logic circuit. The transmission interface provides a first clock signal. The oscillator generates a second clock signal. The correction logic circuit is coupled to the oscillator and the transmission interface, and performs correction operation to count the first clock signal to generate a first clock count value, and count the second clock signal to generate a second clock count value. When the first clock count value is equal to the first count target value, the correction logic circuit stops counting, and calculates a correction value based on the second clock count value and the second count target value. The correction logic circuit outputs the correction value to the oscillator, and the oscillator corrects a frequency of the second clock signal according to the correction value.