Oscillator Clock Trimming Circuit Without CPU-Based Testing
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Solution Overview
Problem
Existing methods for testing and trimming the period of an oscillator clock signal in memory systems require a central processing unit (CPU) and are complex and time-consuming, especially when test equipment limitations are considered.
Innovation Solution
A clock generating circuit comprising an oscillator, clock counter, finite state machine, and non-volatile memory that allows independent testing of the oscillator clock signal by counting and comparing values to determine a final trim value, enabling the oscillator to output a signal with a target period without relying on a CPU, and can be implemented in a system with multiple chips connected in parallel for efficient testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a CPU-based subsystem is used to test the oscillator, then the testing can be performed with existing system resources, but the test complexity and time increase significantly
Solution Approach 1:
The patent separates the oscillator testing function from the CPU-based subsystem by implementing a dedicated testing circuit within the memory device. This segmentation allows the oscillator to be tested independently using local resources (counter, comparator, trim circuit) rather than relying on the external CPU subsystem, thereby reducing test complexity and time while maintaining manufacturing ease
Solution Approach 2:
The patent introduces an intermediary testing circuit that acts as a mediator between the oscillator and the external test environment. This circuit includes a counter, comparator, and trim circuit that collectively perform the oscillation period measurement and adjustment without requiring the CPU subsystem, thus reducing both test complexity and dependency on external processing resources
2Adaptability or versatility
If a CPU-based subsystem is used to test the oscillator, then existing system resources can be utilized, but the test time becomes excessive
Solution Approach 1:
The patent implements preliminary action by pre-configuring the testing circuit with a counter and comparator that can immediately measure the oscillator period without waiting for CPU intervention. The trim circuit is also pre-positioned to make real-time adjustments, enabling the entire testing process to complete in a single clock cycle rather than requiring prolonged CPU-based measurement and iteration
Solution Approach 2:
The oscillator testing function serves itself through the integrated counter, comparator, and trim circuit that are all contained within the memory device. This self-service capability eliminates the need for external CPU subsystem involvement, dramatically reducing test time while still utilizing available on-chip resources for the measurement process
3Device complexity
If the oscillator period is not trimmed, then the circuit operation is simpler, but the clock signal period accuracy deteriorates
Solution Approach 1:
The patent applies parameter changes by introducing a trim circuit that can dynamically adjust the oscillator period based on measured values. The trim circuit modifies the clock signal parameters (period/frequency) by adding or removing cycles based on comparison between the actual count and target count, thereby achieving precise period control without significantly increasing overall circuit complexity
Solution Approach 2:
The patent implements feedback through the comparator that continuously compares the actual clock signal count with the target count and feeds this information back to the trim circuit. This feedback mechanism enables automatic adjustment of the oscillator period to achieve accurate timing, balancing the need for precision with acceptable circuit complexity
Data Source
AI summary
A clock generating circuit includes an oscillator, a clock counter, a finite state machine, and a non-volatile memory. The oscillator outputs an oscillator clock signal having a period based on a trim value. The clock counter counts the oscillator clock signal for a reference time. The finite state machine obtains the count value of the counted oscillator clock signal from the clock counter, and in a test mode, compares the count value with a target count value and changes the trim value based on the comparison result and determines a final trim value based on the changed trim value. The non-volatile memory stores the final trim value that is determined.