Relaxation Oscillator Comparator With Reduced Transition Delay
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Solution Overview
Problem
Relaxation oscillator circuits face challenges in achieving rapid response times without incurring large quiescent currents, which affect the accuracy and frequency of clock signals due to inherent transition delays in comparators.
Innovation Solution
The use of bias current transistors with regulating inputs and transition time reduction transistors, along with current mirror control and output transistors, reduces transition delays while maintaining low quiescent currents by optimizing transistor configurations and ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If comparators are designed to have rapid response times, then transition delays are reduced, but quiescent currents become relatively large and undesirable
Solution Approach 1:
The patent implements dynamic current control where the quiescent current is adjusted based on operational requirements. The bias current transistor receives a regulating input that dynamically adjusts the current level, allowing the system to use higher current only when rapid response is needed and lower current during normal operation, thus resolving the contradiction between response speed and power consumption
Solution Approach 2:
The patent changes the operating parameters of the comparator by introducing a regulating input to the bias current transistor. This allows the quiescent current parameter to be varied according to the specific application needs, enabling optimization of both transition delay and power consumption by selecting appropriate current levels for different operating conditions
2Use of energy by moving object
If comparators use inherent transition delays, then quiescent currents are reduced, but the upper limits and accuracy of oscillator frequency are affected
Solution Approach 1:
The patent uses dynamic current regulation to maintain high current levels during transition periods when accuracy is critical, while allowing lower current levels during stable operation. This dynamic adjustment ensures that frequency accuracy is maintained without continuously consuming high quiescent current
Solution Approach 2:
The regulating input to the bias current transistor prepares the comparator by pre-establishing appropriate current levels before transitions occur. This preliminary action ensures that when frequency measurement or comparison is needed, the comparator is already optimized for high accuracy without requiring continuously high current consumption
Data Source
AI summary
A relaxation oscillator has a comparator that includes first through third bias current transistors coupled to a first supply rail. First and second input transistors form a pair of parallel coupled transistors connected to the first bias current transistor. A first current mirror control transistor connects the first input transistor to a second supply rail. A first current mirror output transistor is coupled to the first current mirror control transistor, and connects the second bias current transistor to the second supply rail. A second current mirror control transistor connects the second input transistor to the second supply rail. A second current mirror output transistor is coupled to the second current mirror control transistor, and connects the third bias current transistor to the second supply rail. A transition time reduction transistor, coupled across the third bias current transistor, is coupled to the second bias current transistor, and provides a comparator output.