Digitally Controlled Oscillator With Configurable DAC Bandwidth
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Solution Overview
Problem
FMCW radar systems require a low noise, highly linear chirp signal with fast settling time, but CMOS deep-submicron process devices face challenges with increased DAC noise and oscillator gain due to lower supply voltage compared to SiGeCmos process devices, necessitating a solution to enhance frequency accuracy and reduce noise contributions.
Innovation Solution
A digitally controlled oscillator with a filtering DAC component and a voltage-controlled oscillator (VCO) featuring a configurable capacitive load, allowing for adjustable filtering bandwidth to minimize DAC noise during the chirp phase and reduce settling time during the reset phase, implemented within a phase-locked loop for FMCW radar systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a filtering DAC component with configurable capacitive load is used, then DAC noise is reduced during chirp phase, but device complexity increases
Solution Approach 1:
The capacitive load of the DAC component is made dynamically configurable between different values. During the chirp phase, a first capacitive load value is applied to achieve narrow bandwidth filtering and reduce DAC noise. During the reset phase, a second capacitive load value is applied to enable faster settling time. This dynamic adaptation allows the system to optimize performance for different operational phases without permanent structural complexity.
Solution Approach 2:
The filtering bandwidth of the DAC component is adjusted by changing the capacitive load parameter. By configuring the capacitive load to different values (first value during chirp phase, second value during reset phase), the system changes the filtering characteristics to match the requirements of each phase, thereby reducing noise when needed while maintaining fast response when required.
2Measurement precision
If oscillator gain is increased five times in CMOS deep-submicron process devices, then frequency accuracy is improved, but DAC noise contribution increases
Solution Approach 1:
A configurable capacitive load is introduced as an intermediary element between the DAC and VCO. This capacitive load acts as a adjustable filter that can be configured to different values depending on the operational phase. During the chirp phase, it filters out DAC noise while allowing the increased oscillator gain to improve frequency accuracy, thereby mediating between the conflicting requirements of noise reduction and accuracy improvement.
Solution Approach 2:
The capacitive load parameter is changed based on the operational phase. During the chirp phase, a larger capacitive load value is used to filter DAC noise, enabling the system to tolerate higher oscillator gain without excessive noise. During the reset phase, a smaller capacitive load value is used to allow faster response. This parameter change strategy resolves the contradiction between noise reduction and accuracy improvement.
3Object-generated harmful factors
If filtering bandwidth is narrowed to reduce DAC noise, then noise performance is improved, but settling time increases
Solution Approach 1:
The filtering bandwidth of the DAC component is made dynamic through configurable capacitive load. During the chirp phase, the capacitive load is set to a first value that provides narrow bandwidth filtering, reducing DAC noise. During the reset phase, the capacitive load is switched to a second value that widens the bandwidth, enabling faster settling time. This temporal separation of filtering requirements resolves the contradiction between noise reduction and settling speed.
Solution Approach 2:
The system operates in periodic cycles alternating between chirp phase and reset phase. During each chirp phase, narrow bandwidth filtering is applied to reduce noise. During each reset phase, wide bandwidth is applied to enable fast settling. This periodic switching of filtering characteristics allows the system to achieve both low noise and fast settling time by matching the filtering bandwidth to the current operational phase requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a low-noise, highly linear chirp signal with improved settling time, effectively addressing the noise and accuracy requirements of FMCW radar systems while being compatible with CMOS deep-submicron process devices, enhancing the performance of FMCW radar systems.
Implementation Method 1
one or more configurable capacitive load component(s) to which the control voltage is applied such that a filtering bandwidth of the DAC component is configurable
Data Source
Figure 1
Figure 2(a)~2(b)
Figure 3~4
AI summary
A digitally controlled oscillator comprising a filtering digital to analogue converter, DAC, component and a voltage controlled oscillator, VCO, component comprising at least one control terminal arranged to receive a control voltage output by the DAC component; wherein the DAC component comprises a voltage generation component arranged to generate the control voltage and at least one configurable capacitive load component to which the control voltage is applied such that a filtering bandwidth of the DAC component is configurable by way of the at least one configurable capacitive load component.