Oscillator Current Limiting for Clock Frequency Suppression
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Solution Overview
Problem
Conventional oscillator circuits using constant current circuits face issues where a drop in supply voltage can lead to an abnormal increase in output current, resulting in an excessively high clock signal frequency, which may not be guaranteed to operate within the required limits.
Innovation Solution
Incorporating a current limiting circuit between the constant current circuit and the oscillator to regulate the output current and establish an upper limit for the clock signal frequency, preventing it from exceeding a predetermined value by adjusting the current flow through transistors and resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the supply voltage drops below the lower limit of the guaranteed operational range, then the output current of the constant current circuit abnormally increases, but this causes the clock signal frequency to become excessively high and potentially exceed required limits
Solution Approach 1:
A current limiting circuit is introduced as an intermediary component between the constant current circuit and the oscillator. This mediator limits the output current when the supply voltage drops, preventing the clock signal frequency from exceeding predetermined limits while allowing normal operation when voltage is within the guaranteed range.
2Device complexity
If no current limiting circuit is used, then the circuit structure remains simple, but the clock signal frequency cannot be guaranteed to operate within required limits when supply voltage drops
Solution Approach 1:
The current limiting circuit serves as a protective intermediary that adds minimal complexity to ensure frequency reliability. It comprises transistors and resistors configured to limit current flow, providing frequency guarantee without significantly complicating the overall circuit structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The current limiting circuit ensures that the clock signal frequency remains within acceptable limits, ensuring the operation of synchronized circuits by controlling the charging time of capacitors and maintaining the current mirror ratio, even when the supply voltage drops below a certain threshold.
Implementation Method 1
maintaining the current mirror ratio
Implementation Method 2
controlling the current flow through transistors and resistors
Implementation Method 3
controlling the charging time of capacitors
Data Source
AI summary
The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.