Oscillator Clock Gating Using Cycle Counting for Startup Duty Control
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Solution Overview
Problem
Existing oscillators face challenges in maintaining an appropriate clock signal duty during activation, especially under environmental and process changes, such as temperature variations, due to limitations in controlling the output signal through analog processing.
Innovation Solution
A circuit device with an oscillation circuit, a clock signal output circuit, and an output control circuit that includes a counter circuit and a count enable signal generation circuit, which starts the counting process based on the oscillation circuit's output signal, ensuring an appropriate clock signal is output by controlling the output enable signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If analog processing is used to control the output of a clock signal by integrating an oscillation signal, then the circuit complexity is reduced, but the ability to cope with wide environmental temperature changes and process variations deteriorates, resulting in inability to output an appropriate clock signal satisfying specifications during activation
Solution Approach 1:
The patent replaces the analog integration circuit with a digital counter circuit. Instead of using analog integration to control clock signal output, the invention uses a counter to count oscillation signal cycles and compares the count value with a reference value to determine when to output the clock signal. This substitution of analog processing with digital processing enables the system to maintain appropriate clock signal duty cycle under wide environmental temperature changes and process variations, while keeping the circuit structure relatively simple.
2Measurement precision
If the oscillation signal amplitude is increased to ensure sufficient signal level, then the signal quality improves, but the integration voltage reaches predetermined voltage too quickly, causing the clock signal duty to deviate from specifications during activation
Solution Approach 1:
The patent implements a feedback mechanism where the counter circuit continuously counts the oscillation signal cycles and compares the accumulated count value with a predetermined reference value. The clock signal output is controlled based on this comparison, ensuring that the output duty cycle remains accurate even when the oscillation signal amplitude varies. This feedback-based digital control replaces the open-loop analog integration approach, preventing duty cycle deviation during activation.
3Speed
If a counter is used to control activation timing of the oscillation circuit, then the activation speed improves, but the counter is only used for making activation earlier without ensuring appropriate clock signal duty during activation
Solution Approach 1:
The patent extends the functionality of the counter circuit beyond simple activation timing control. The same counter that tracks activation timing is also used to determine the appropriate moment to output the clock signal by comparing its count value with a reference value. This multi-functional use of the counter ensures both fast activation and appropriate clock signal duty cycle during activation, eliminating the need for separate control mechanisms.
Data Source
AI summary
A circuit device includes an oscillation circuit, a clock signal output circuit that outputs a clock signal based on an output signal from the oscillation circuit, and an output control circuit. The output control circuit includes a counter circuit that performs a counting process on the basis of the output signal from the oscillation circuit, and a count enable signal generation circuit that outputs a count enable signal for the counter circuit. The counter circuit starts the counting process when the count enable signal becomes active, and outputs an output enable signal for the clock signal to the clock signal output circuit on the basis of a result of the counting process.