Current-Controlled Oscillator Feedback for Stable On-Chip Clocks
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Solution Overview
Problem
Conventional oscillator arrangements in semiconductor devices are not cost-effective for smaller systems due to the need for external reference crystal clocks and are sensitive to temperature and power supply variations, leading to frequency instability.
Innovation Solution
An oscillator arrangement comprising a current-controlled oscillator, frequency-to-voltage converter, and operational amplifier, where both feedback and reference voltages are generated from the same supply voltage, eliminating the need for additional amplifiers and reducing power consumption, and using a trimming resistor to adjust frequency without digital-to-analog converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL is used for clock generation, then frequency stability is improved, but device complexity and cost increase due to external reference crystal requirements
Solution Approach 1:
The invention extracts and eliminates the external reference crystal requirement from the clock generation system. By using an on-chip reference oscillator combined with a phase-frequency detector and feedback mechanism, the system achieves PLL-like frequency stability without needing external crystal components, thereby reducing device complexity and cost.
Solution Approach 2:
The oscillator arrangement generates its own reference clock signal using an on-chip reference oscillator, making the system self-sufficient. The feedback loop automatically adjusts the VCO frequency to match the desired clock frequency, enabling the system to self-regulate without external reference components.
2Adaptability or versatility
If conventional DAC is used for frequency control, then frequency adjustment is achieved, but area consumption increases significantly
Solution Approach 1:
The invention replaces the conventional DAC (digital-to-analog converter) mechanism with a direct digital control approach. Instead of converting digital trimming bits to analog voltage through a DAC, the system uses a feedback loop with a phase-frequency detector that directly adjusts the VCO frequency based on digital comparison of the output clock with the reference clock, eliminating the need for large-area DAC circuits.
3Manufacturing precision
If negative feedback loop is used to linearize VCO, then frequency linearity is improved, but sensitivity to supply and temperature variations increases
Solution Approach 1:
The invention creates equipotential conditions by generating both the reference voltage and feedback voltage from the same supply voltage source. This ensures that any supply voltage variations or temperature-induced changes affect both voltages equally, and the differential comparison in the operational amplifier rejects these common-mode variations, making the frequency output insensitive to supply and temperature fluctuations while maintaining linearity through the feedback mechanism.
4Measurement precision
If multiple amplifiers are used for voltage generation, then voltage precision is improved, but power consumption increases
Solution Approach 1:
The invention merges the functions of multiple voltage generation amplifiers into a single operational amplifier. The op-amp simultaneously generates the feedback voltage from the frequency-to-voltage converter output and compares it with the reference voltage, eliminating the need for separate amplifiers and significantly reducing power consumption while maintaining voltage precision through its high-gain feedback mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a stable clock signal insensitive to supply and temperature variations, achieving low-power and low-area performance with reduced area consumption by using common-mode noise rejection and digital trimming of resistors.
Implementation Method 1
The frequency to voltage converter is adapted to generate an output voltage signal (Vout) based on the generated clock signal and based on the supply voltage signal
Implementation Method 2
The operational amplifier is adapted to receive the output voltage signal as a feedback signal at a first (for instance the positive) input terminal and to receive a reference voltage signal (Vref) at a second (for instance the negative) input terminal
Data Source
AI summary
There is provided an oscillator arrangement for generating a clock signal. The oscillator arrangement comprises a current controlled oscillator, a frequency to voltage converter, and an operational amplifier. The oscillator arrangement is connectable to a supply voltage source. In one embodiment, the oscillator arrangement may achieve a stable clock frequency insensitive to supply and temperature variation with low current consumption and low area. This may be achieved by using Vref and Vout as input signals to the operational amplifier, both signals being directly derived from the supply voltage. In a further embodiment, a trimming resistor may be used in the frequency to voltage converter for adjusting the frequency.