Oscillator-Based FLL for Low-Power Clock Lock During Mode Transitions
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Solution Overview
Problem
Existing clock generation technologies in portable devices often require power-hungry phase-locked loops (PLLs) for low-frequency clocks with high jitter, which occupy significant space and consume more power, and lack efficient methods for maintaining clock lock during mode transitions.
Innovation Solution
A frequency-locked loop (FLL) system using a digitally controlled oscillator (DCO) that selectively stops oscillation after a time period, allowing the oscillator to remain in an active mode and adjust control settings to maintain a low-frequency clock with high jitter, enabling smaller design area and reduced power consumption, and allowing for automatic test generation pattern tools in production testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop (PLL) is used to generate low-frequency clocks with high jitter, then clock frequency and quality are improved, but power consumption and device area increase significantly
Solution Approach 1:
The patent changes the fundamental operating parameters of the clock generation system by using a frequency-locked loop (FLL) instead of a phase-locked loop (PLL). The FLL operates at lower frequencies with relaxed timing requirements, allowing high jitter tolerance while consuming significantly less power. This parameter change enables the system to achieve adequate clock quality for low-frequency applications without the power overhead of traditional PLLs.
Solution Approach 2:
The patent extracts and removes the high-power PLL circuitry from the system for applications that can tolerate high jitter. By identifying that certain devices (e.g., digital signal processors playing MP3 songs) can operate adequately with high jitter clocks, the design eliminates the need for power-hungry PLLs in those specific contexts, thereby reducing overall power consumption while maintaining sufficient clock quality.
2Reliability
If a phase-locked loop (PLL) is used to generate low-frequency clocks with high jitter, then clock frequency and quality are improved, but device area occupied increases
Solution Approach 1:
The patent changes the fundamental operating parameters of the clock generation system by using a frequency-locked loop (FLL) instead of a phase-locked loop (PLL). The FLL operates at lower frequencies with relaxed timing requirements, allowing high jitter tolerance while consuming significantly less power. This parameter change enables the system to achieve adequate clock quality for low-frequency applications without the power overhead of traditional PLLs.
Solution Approach 2:
The patent extracts and removes the high-power PLL circuitry from the system for applications that can tolerate high jitter. By identifying that certain devices (e.g., digital signal processors playing MP3 songs) can operate adequately with high jitter clocks, the design eliminates the need for power-hungry PLLs in those specific contexts, thereby reducing overall power consumption while maintaining sufficient clock quality.
3Use of energy by moving object
If a frequency-locked loop (FLL) selectively stops oscillation to reduce power consumption, then power efficiency is improved, but clock stability during mode transitions may deteriorate
Solution Approach 1:
The patent implements periodic action by selectively stopping and restarting the oscillator based on operational requirements. The FLL control logic monitors the operational state and activates the oscillator only when needed, allowing it to remain in active mode for quick restart while consuming minimal power during idle periods. This periodic operation maintains clock stability during transitions by ensuring the oscillator is ready to resume immediately when required.
Solution Approach 2:
The patent applies preliminary action by keeping the oscillator in an active mode with minimal power consumption rather than completely shutting it down. This preliminary state allows the oscillator to resume operation immediately when needed, avoiding the stability issues that would arise from cold startup. The control logic prepares the oscillator in advance by maintaining it in a low-power active state, ensuring rapid and stable recovery when oscillation needs to resume.
Data Source
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AI summary
A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator.