Crystal Oscillator Frequency Adjustment for UDP Clock Synchronization
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Solution Overview
Problem
The integration of different crystal oscillators in transmitting and receiving devices leads to significant differences in clock frequencies, causing data processing delays and potential data loss due to overflow, necessitating large-capacity SDRAM for caching, which increases transmission latency.
Innovation Solution
A method and receiving device that adjusts the clock frequency of the crystal oscillator based on the difference between data volume and a preset threshold, using a cache to store UDP packets and employing a PID algorithm to maintain synchronization, thereby reducing hardware costs and achieving ultra-low latency transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different crystal oscillators are integrated in transmitting and receiving devices, then device independence and hardware flexibility are improved, but clock frequency synchronization deteriorates, causing data processing delays and potential data loss
Solution Approach 1:
The patent implements a feedback mechanism where the receiving device monitors the clock frequency difference between transmitting and receiving devices, and adjusts its crystal oscillator frequency accordingly. The system calculates the frequency difference based on data volume in cache and feeds this information back to the crystal oscillator control module, which automatically adjusts the oscillator frequency to maintain synchronization, thus resolving the contradiction between device independence and clock frequency synchronization.
Solution Approach 2:
The patent changes the operating parameter (frequency) of the crystal oscillator dynamically. By adjusting the crystal oscillator frequency in the receiving device based on the monitored frequency difference and cache data volume, the system adapts the oscillator parameters to maintain synchronization despite using different hardware components, thereby resolving the contradiction between device independence and synchronization reliability.
2Reliability
If large-capacity SDRAM is used to store or cache more data, then data loss due to overflow is prevented, but transmission delay increases
Solution Approach 1:
The patent implements dynamic cache management where the cache capacity and data retention time are adjusted in real-time based on the clock frequency synchronization status. When synchronization is good, cache capacity is reduced; when synchronization deteriorates, cache capacity is increased. This dynamic adjustment prevents data loss while minimizing transmission delay, resolving the contradiction between reliability and time loss.
Solution Approach 2:
The patent uses partial caching strategy where only the necessary amount of data is cached based on the current synchronization status, rather than pre-allocating large cache capacity. The system caches just enough data to handle frequency variations, avoiding excessive caching that would increase delay, thus resolving the contradiction between preventing data loss and minimizing transmission delay.
3Measurement precision
If clock frequency adjustment is implemented to maintain synchronization, then data transmission accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements a self-service synchronization mechanism where the receiving device automatically monitors its own clock frequency accuracy, calculates the frequency difference, and adjusts its crystal oscillator without external intervention. The system uses its own cache data volume information to determine the frequency adjustment needed, making the device self-regulating and reducing the need for complex external control mechanisms, thus resolving the contradiction between transmission accuracy and device complexity.
Data Source
AI summary
Disclosed are a method and a receiving device for clock frequency synchronization. The method includes the following. A user datagram protocol (UDP) packet is obtained by a receiving device. A value of the data volume of the UDP packet in the cache and a first value are performed, by the receiving device, an operation to obtain the absolute value of the difference between the value of the data volume and the first value. When the absolute value is greater than the preset threshold, a clock frequency of the crystal oscillator in the receiving device is adjusted to obtain a target clock frequency, where after the clock frequency of the crystal oscillator is adjusted, the absolute value of the difference is less than or equal to the preset threshold. The receiving device maintains clock frequency synchronization between the receiving device and the transmitting device based on the target clock frequency.