Oscillator IC Layout With Vertical Vias for Low Parasitic Resistance
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Solution Overview
Problem
Integrated circuit apparatuses face challenges in heat generation efficiency due to parasitic resistance, which reduces current flow and heat generation performance, particularly in diffusion layers between power supply and ground pads.
Innovation Solution
The integrated circuit apparatus includes a layout design with via wires that reduce parasitic resistance by creating short, orthogonal current paths between pads and transistors, allowing for increased current flow and improved heat generation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional layout design is used with long current paths between pads and transistors, then device complexity is reduced, but parasitic resistance increases causing current decrease and reduced heat generation efficiency
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing by positioning transistor drains directly beneath power supply pads and transistor sources directly beneath ground pads. This vertical alignment through via wires creates orthogonal current paths that dramatically reduce parasitic resistance while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
2Loss of energy
If via wires are used to create short orthogonal current paths, then parasitic resistance is reduced and heat generation efficiency is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The current path is segmented into distinct vertical segments: power supply pad to drain via wire, drain to source through transistor channel, and source to ground pad via wire. This segmentation allows each component to be optimized independently while maintaining overall low parasitic resistance, and enables standard fabrication processes to be used for each segment.
Solution Approach 2:
The patent applies different structural qualities to different regions: via wires are used specifically at pad connections where resistance reduction is most critical, while standard planar transistor structures are maintained in the active device region. This localized optimization reduces parasitic resistance where it matters most without complicating the overall manufacturing process.
3Reliability
If longer diffusion layers are used to connect pads to transistors, then ease of manufacture is improved, but parasitic resistance increases causing current decrease
Solution Approach 1:
The patent eliminates long planar diffusion paths by transitioning to vertical connections through via wires. The drain and source diffusion regions are positioned directly beneath the pads in the vertical dimension, creating short orthogonal current paths that maintain manufacturing simplicity while dramatically reducing parasitic resistance and ensuring stable current flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces parasitic resistance, enhancing heat generation efficiency and preventing current decrease, while also being resistant to electromigration and allowing for a compact, high-current-capable integrated circuit.
Implementation Method 1
a first drain coupling via wire that is a via wire electrically coupling the first pad to the first drain, and a first source coupling via wire that is a via wire electrically coupling the second pad to the first source
Implementation Method 2
heat generating circuit including a heat generating transistor coupled between a power supply pad and a ground pad
Data Source
AI summary
An integrated circuit apparatus includes a first pad to which one of a power supply voltage and a ground voltage is supplied, a second pad to which the other of the power supply voltage and the ground voltage is supplied, a first transistor having a first gate to which a temperature control signal is input, a first drain electrically coupled to the first pad, and a first source electrically coupled to the second pad, a first drain coupling via wire that is a via wire electrically coupling the first pad to the first drain, and a first source coupling via wire that is a via wire electrically coupling the second pad to the first source. In plan view, the first drain overlaps the first pad and the first source overlaps the second pad.