Piezoelectric Oscillator Layout for Low Phase Noise PLL Output
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Solution Overview
Problem
Existing piezoelectric oscillators with integrated oscillation circuits and fractional N-PLL circuits suffer from increased phase noise and phase jitter due to strong magnetic connections between wiring components, particularly when these components are close to each other, leading to issues with integer boundary spurious effects.
Innovation Solution
The vibrator device incorporates a semiconductor substrate with a fractional N-PLL circuit and output terminal positioned on opposite sides to prevent overlap, utilizing a bonding layer as a shield to suppress electromagnetic connections and include non-overlapping wirings and inductors to minimize phase noise and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the wiring that electrically couples the vibrating element and the oscillation circuit and the wiring that electrically couples the fractional N-PLL circuit and the output terminal are placed close to each other for miniaturization, then the device size is reduced, but the magnetic connection between the wirings becomes stronger causing phase noise and phase jitter to worsen
Solution Approach 1:
The patent resolves the contradiction by transitioning from a two-dimensional planar layout to a three-dimensional stacked configuration. The first wiring is disposed on the first surface of the semiconductor substrate, while the second wiring is disposed on the second surface (opposite side) of the substrate. This spatial separation in the thickness direction prevents overlapping in plan view, thereby reducing magnetic coupling between the wirings while maintaining miniaturization benefits.
Solution Approach 2:
The semiconductor substrate acts as an intermediary element that physically separates the first wiring and second wiring. By placing the wirings on opposite surfaces of the substrate, the substrate serves as a mediating structure that reduces direct magnetic interaction between the wirings, thus suppressing phase noise and phase jitter while allowing compact device design.
2Ease of manufacture
If the output terminal is positioned to overlap the wiring in plan view to simplify layout, then manufacturing is easier, but electromagnetic connection between the wiring and output terminal increases causing integer boundary spurious effects
Solution Approach 1:
The patent eliminates the overlapping configuration by utilizing the third dimension (thickness direction) for spatial separation. The output terminal is positioned on the second surface of the semiconductor substrate, while the wiring is on the first surface, ensuring no overlap in plan view. This dimensional approach simplifies layout planning while simultaneously preventing harmful electromagnetic connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively separates electromagnetic connections, reducing the impact of integer boundary spurious and phase noise, thereby enhancing the stability of the circuit's output signals.
Implementation Method 1
utilizing a bonding layer as a shield to suppress electromagnetic connections
Implementation Method 2
A piezoelectric oscillator described in JP-A-2017-139717 includes: a silicon first substrate; a circuit formed at a front surface side of the silicon first substrate and an external electrode coupled to the circuit; a vibrating element mounted at a back surface of the silicon first substrate
Data Source
AI summary
There is provided a vibrator device including: a vibrator element; a semiconductor substrate having a first surface on which the vibrator element is disposed and a second surface positioned on an opposite side of the first surface; a fractional N-PLL circuit disposed at the second surface; a wiring that is disposed at the first surface and electrically couples the vibrator element and the fractional N-PLL circuit; and an output terminal that is disposed at the second surface side of the semiconductor substrate, is electrically coupled to the fractional N-PLL circuit, and outputs a signal from the fractional N-PLL circuit, in which the output terminal does not overlap the wiring in a plan view along a thickness direction of the semiconductor substrate.