Crystal Oscillator Load Switching for Noise-Resistant Amplitude Control
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Solution Overview
Problem
Existing crystal oscillator circuits, particularly Pierce oscillators, face challenges in achieving a wide frequency pulling range, high immunity to noise, reduced power dissipation, and minimizing crystal degradation while maintaining high negative impedance and low phase noise.
Innovation Solution
A crystal oscillator circuit with a degenerated common source amplifier configuration, a differential pick-up stage, and a capacitive load stage that can be selectively switched using digital configuration signals to adapt to different crystals, reducing noise injection and power consumption, and enhancing adaptability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bias current is controlled by an amplitude control circuit with high conversion gain, then the negative impedance can be adjusted to match the crystal ESR, but the phase noise performance severely degrades due to amplified noise from the ACC
Solution Approach 1:
The patent introduces a current mirror circuit as an intermediary between the amplitude control circuit and the amplifying transistor. The ACC generates a control current that is mirrored to adjust the bias current of the amplifying transistor, rather than directly controlling the transistor current. This intermediary approach reduces the conversion gain in the noise-sensitive path while maintaining the ability to adjust negative impedance to match crystal ESR.
2Reliability
If a conventional Pierce oscillator circuit is used, then stable clock signals can be generated, but the circuit has limited immunity to substrate noise and cross-talking when implemented on integrated circuits
Solution Approach 1:
The patent employs asymmetric circuit topology with dedicated noise filtering paths and selective coupling arrangements. The amplifying transistor is coupled to the crystal through specific capacitor configurations that create asymmetric impedance paths, providing differential immunity to substrate noise and cross-talking while maintaining stable oscillation generation.
3Reliability
If the crystal oscillator circuit is designed for high negative impedance, then the oscillation can be maintained, but the power dissipation increases and crystal degradation accelerates
Solution Approach 1:
The patent implements dynamic control of the bias current through the amplitude control circuit that monitors oscillation amplitude and adjusts the bias current accordingly. This dynamic adjustment allows the circuit to maintain sufficient negative impedance for oscillation while minimizing excess power dissipation and reducing crystal degradation by operating at optimal current levels rather than fixed high current.
Data Source
AI summary
A crystal oscillator circuit includes a capacitive load stage coupled to a crystal; an amplifier stage including an amplifying transistor coupled to the crystal and to the capacitive load stage for establishing an oscillation signal at the amplifier stage output and a bias generator stage coupled to the amplifying transistor; an amplitude control stage to control the amplitude of the oscillation signal; a pick-up stage coupled to the amplifier stage and to the crystal to generate an oscillator output signal. The bias generator stage is configured as a degenerated common source amplifier.