Oscillator Mid-Power Switching for Low-Jitter Clock Efficiency
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Solution Overview
Problem
Modern communication devices face increased power consumption due to high-frequency crystal oscillator blocks, which is wasteful when operating at legacy rates or in scenarios that do not require high-quality clock signals, leading to reduced battery life and competitiveness, especially in battery-powered platforms.
Innovation Solution
Implementing a mid power mode for the oscillator circuitry that switches between two discrete power states based on the device's operational mode, allowing for reduced power consumption while maintaining sufficient clock signal quality, and transitioning between these states quickly to support both high-end connectivity and power-optimized operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the current supplied to the XO block is increased to meet higher jitter specifications, then the quality of clock signals is improved, but the power consumption is increased
Solution Approach 1:
The patent implements dynamic power management by enabling the XO block to switch between multiple power modes (low power mode and high power mode) based on operational requirements. The system dynamically adjusts the current supplied to the XO block, providing high current only when high-quality clock signals are needed, and reducing current during normal operations, thereby resolving the contradiction between maintaining clock signal quality and reducing power consumption.
Solution Approach 2:
The patent changes the operational parameters of the XO block by introducing multiple power modes with different current levels. The system can transition between a first power mode with lower current consumption and a second power mode with higher current consumption, allowing the parameters of power supply to be adjusted according to the quality requirements of clock signals for different applications.
2Reliability
If the current supplied to the XO block is increased to meet modern communication standards, then the jitter specification is satisfied, but the battery life is reduced
Solution Approach 1:
The system dynamically adapts the power supply to the XO block based on the operational mode. During modern communication operations requiring low jitter, the system provides high current to satisfy jitter specifications. During legacy rate operations or when high-quality clock signals are not required, the system switches to low power mode with reduced current, thereby extending battery life while maintaining reliability when needed.
Solution Approach 2:
The patent implements periodic switching between power modes based on operational requirements. The system transitions between high power mode and low power mode periodically or event-driven, providing high current only during intervals when modern communication standards are active, and reducing power consumption during intervals when legacy operations are performed, thus balancing jitter specification compliance with battery life extension.
3Measurement precision
If the oscillator operates in high power mode continuously, then the clock signal quality is maintained, but the power consumption is unnecessarily increased during legacy rate operations
Solution Approach 1:
The patent applies partial action by providing high-quality clock signals only when necessary for modern communication standards. During legacy rate operations, the system uses a lower power mode that provides sufficient but not excessive clock signal quality, eliminating unnecessary energy consumption while maintaining adequate performance for the operational requirements.
Data Source
AI summary
Methods, systems, and circuitries are provided to generate clock signals of different qualities in a device. A method includes determining whether the device is operating in a mid power mode or a high power mode. In response to determining that the device is operating in the mid power mode, oscillator circuitry is controlled to cause the oscillator circuitry to consume a lower amount of power, such that the oscillator circuitry generates a lower quality clock signal. In response to determining that the device is operating in the high power mode, the oscillator circuitry is controlled to cause the oscillator circuitry to consume a higher amount of power, such that the oscillator circuitry generates a higher quality clock signal. The lower amount of power and the higher amount of power are different from one another.