Local Oscillator Path Synchronization Using a Golden Phase Reference
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Solution Overview
Problem
Phase synchronization among local oscillator paths in oscillator-operated circuits is challenging due to phase ambiguities introduced by dividers, especially in fractional-N PLLs, which can lead to misalignment of transmission signals in MIMO systems, requiring significant wiring or multiple PLLs with potential incoherent states.
Innovation Solution
A system utilizing a counter to generate a 'golden' phase reference signal that synchronizes oscillator phases across multiple PLLs, incorporating a sigma-delta modulator and multi-modulus divider, with minimal hardware overhead, to align rising edges and correct phase errors, ensuring synchronization even across different circuit chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple PLLs are used for different MIMO channels, then phase synchronization can be achieved through shared reference clock, but individual dividers at each PLL introduce phase ambiguities resulting in incoherent states
Solution Approach 1:
A dedicated synchronization counter is introduced as an intermediary component that receives the reference clock and generates synchronized enable signals distributed to all PLLs. This mediator ensures that all dividers across multiple PLLs operate in coherent states by providing a unified timing reference, thereby eliminating phase ambiguities without requiring complex inter-PLL communication or additional wiring between PLL circuits.
Solution Approach 2:
The synchronization counter serves multiple functions simultaneously: it acts as a reference clock divider, generates enable signals for multiple PLLs, provides timing synchronization for dividers across different channels, and maintains coherent states for all MIMO paths. This multi-functional approach consolidates what would otherwise require separate synchronization circuits for each PLL into a single universal synchronization unit.
2Reliability
If a single PLL is used to track and lock phases for all MIMO channels, then phase synchronization is achieved, but significant wiring is required
Solution Approach 1:
The synchronization function is segmented from the PLL structures themselves and placed in a dedicated synchronization counter unit. Each PLL receives only the essential synchronized enable signal from this counter, eliminating the need for extensive inter-PLL wiring. The segmentation separates the synchronization generation function from the frequency synthesis function, allowing independent optimization of each.
3Adaptability or versatility
If dividers are used in fractional-N PLLs to achieve frequency multiplication, then frequency synthesis is achieved, but phase ambiguity is introduced among different PLLs
Solution Approach 1:
The synchronization counter provides a feedback mechanism by generating enable signals that are distributed to all PLLs and dividers in the system. This feedback ensures that all frequency synthesis operations are coordinated to a common timing reference, maintaining phase coherence across all MIMO channels while preserving the frequency multiplication capability of the fractional-N PLLs.
Data Source
AI summary
Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.