High-Frequency Oscillator Reducing PLL Noise

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Solution Overview

Problem

Existing PLL circuits face challenges in reducing noise, particularly reference leak noise and DSM noise, due to limitations in oscillation frequency and phase comparison frequency, which hinder the accuracy of the clock signal generated.

Innovation Solution

The oscillator employs a quartz crystal resonator with an oscillation frequency of at least 200 MHz and a phase comparison frequency of at least 200 MHz, along with a fractional-N type PLL circuit, to increase the phase comparison frequency and operate the delta sigma modulation circuit at higher frequencies, thereby shifting noise out of the measurement range and reducing in-band noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a quartz crystal resonator with oscillation frequency of approximately 50 MHz is used in the PLL circuit, then the circuit can operate at lower frequencies with simpler design, but the phase comparison frequency is limited to approximately 100 to 120 MHz at maximum, which prevents effective noise reduction

Engineering Contradiction:

Improveclock signal accuracyVSAvoidcircuit design complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the fundamental parameter of the quartz crystal resonator's oscillation frequency from the conventional 50 MHz to a higher frequency of 200 MHz or more. This parameter change enables the phase comparison frequency to be 200 MHz or more, which effectively shifts noise components out of the measurement range and achieves superior noise reduction while maintaining circuit simplicity

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

Instead of trying to reduce noise by lowering frequencies or adding complex noise filtering circuits, the patent inverts the approach by raising the phase comparison frequency to 200 MHz or more. This inversion naturally pushes noise components to higher frequencies where they can be more easily filtered, achieving noise reduction without increasing circuit complexity

Inventive Principle:

Principle #13The other way round (Inversion)

2Object-generated harmful factors

If the phase comparison frequency is increased to reduce reference leak noise and DSM noise, then noise reduction performance improves, but the oscillation frequency requirements become more stringent

Engineering Contradiction:

Improvereference leak noise and DSM noiseVSAvoidoscillation frequency stability

Core Design Contradiction:

Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent specifies that the quartz crystal resonator should have an oscillation frequency of 200 MHz or more, which directly addresses the noise reduction requirement. This parameter change ensures that both reference leak noise and DSM noise are shifted to frequencies that can be effectively filtered, while the high-stability quartz crystal resonator maintains reliable oscillation at this higher frequency

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If a fractional-N type PLL circuit is used to set the operation range of the voltage control oscillation circuit, then the frequency setting flexibility improves, but the delta sigma modulation operates at lower frequencies which limits noise reduction effectiveness

Engineering Contradiction:

Improvefrequency setting flexibilityVSAvoidnoise reduction effectiveness

Core Design Contradiction:

Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent combines the fractional-N type PLL circuit's frequency flexibility with a fundamentally higher phase comparison frequency of 200 MHz or more. This allows the delta sigma modulation to operate at the higher frequency, pushing noise components out of the measurement range while retaining the frequency setting flexibility provided by the fractional-N architecture

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces noise in the PLL circuit by increasing the phase comparison frequency, minimizing reference leak noise and DSM noise, and allowing for a more compact circuit design with improved noise reduction and accuracy.

Implementation Method 1

an oscillation circuit that generates a reference clock signal by oscillating the quartz crystal resonator

Methodology Applied

Scientific EffectPiezoelectric effect: Piezoelectric Effect

Data Source

PatentUS10797711B2Oscillator, electronic apparatus, and vehicle

Publication Date: 2020.10.06 SEIKO EPSON CORP

AI summary

An oscillator includes a quartz crystal resonator and a circuit device, and the circuit device includes an oscillation circuit and a PLL circuit. The PLL circuit includes a phase comparison circuit that performs a phase comparison between the reference clock signal and a feedback clock signal, a control voltage generation circuit that generates a control voltage based on a result of the phase comparison, and a voltage control oscillation circuit that generates a clock signal having a frequency corresponding to the control voltage, and a frequency division circuit that divides a frequency of the clock signal and outputs the feedback clock signal. An oscillation frequency of the quartz crystal resonator is higher than or equal to 200 MHz, and a phase comparison frequency of the phase comparison circuit is higher than or equal to 200 MHz.