Oscillator Pull-Up Circuit for Low-Voltage Clock Integrity
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Solution Overview
Problem
Conventional oscillators face difficulties in generating a stable clock signal when the power source voltage falls below a specified threshold, leading to extended low-to-high transitions and reduced current drivability of PMOS transistors, which affects the amplitude, period, and phase of the clock signal.
Innovation Solution
The oscillator design includes a reference voltage generator, output voltage generators, and a logic combination circuit, with pull-up circuits to ensure that one output voltage goes high before the other goes low, utilizing PMOS transistors to rapidly transition the output voltage and maintain clock signal integrity even at reduced power source voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If power source voltage falls below specified threshold, then oscillator can still operate at reduced voltage, but low-to-high transition time extends and current drivability of PMOS transistor reduces
Solution Approach 1:
A pull-up circuit is introduced as an intermediary component between the PMOS transistor and the output node. This pull-up circuit actively assists in pulling the output voltage high, compensating for the reduced current drivability of the PMOS transistor when operating at reduced power source voltages, thereby maintaining acceptable transition times across a wider voltage range.
Solution Approach 2:
The invention changes the operating parameters of the oscillator by introducing a pull-up circuit that modifies the voltage transition characteristics. This allows the oscillator to maintain proper clock signal specifications (amplitude, period, phase) even when the power source voltage drops below the originally specified threshold, effectively expanding the operational voltage range.
2Adaptability or versatility
If power source voltage falls below specified threshold, then oscillator can operate at reduced voltage, but clock signal specifications (amplitude, period, phase) deteriorate
Solution Approach 1:
The pull-up circuit serves as a mediator that ensures the output voltage reaches the required high level reliably, even when the PMOS transistor's current drivability is reduced at lower power source voltages. This maintains the amplitude and other specifications of the generated clock signal across a broader voltage range.
Solution Approach 2:
By introducing the pull-up circuit, the invention changes the voltage transition parameters to ensure that clock signal specifications (amplitude, period, phase) remain within acceptable limits even when operating at reduced power source voltages, thereby maintaining reliability across varying voltage conditions.
3Loss of energy
If PMOS transistor current drivability reduces at lower voltage, then power consumption decreases, but transition speed and signal integrity deteriorate
Solution Approach 1:
The pull-up circuit is introduced as a mediator that compensates for the reduced transition speed caused by lower PMOS transistor current drivability at reduced voltages. This allows the system to operate at lower power consumption while maintaining acceptable transition speeds through the combined action of the PMOS transistor and the pull-up circuit.
Data Source
AI summary
Disclosed is an oscillator including a reference voltage generator generating a reference voltage, and a logic combination circuit generating complementary first and second internal clock signals in response to the reference voltage and complementary first and second output voltages. One of the first and second output voltages—the one going high—is provided to the logic combination circuit before the other one of the first and second output voltages—the one going low.