Crystal Oscillator Reset Pulses for Lower Phase Noise
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Solution Overview
Problem
Existing crystal oscillators face challenges in reducing phase noise of the reference clock without introducing side effects, which affects the overall performance of electronic systems.
Innovation Solution
A crystal oscillator design incorporating a crystal oscillator core circuit, a bias circuit, a pulse wave buffer, and a phase noise reduction circuit that generates a reset signal without calibrating the reset pulse to the zero-crossing point of the sinusoidal wave, providing an AC ground path to reset the bias voltage and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuits are added to reduce phase noise of the crystal oscillator, then phase noise performance is improved, but device complexity increases
Solution Approach 1:
The invention segments the phase noise reduction function into a dedicated reset circuit that operates independently from the main oscillator core. The reset circuit generates reset signals to periodically discharge the bias circuit, separating the noise reduction function from the signal generation function. This allows phase noise improvement without significantly increasing overall system complexity.
Solution Approach 2:
The invention introduces a reset signal as an intermediary mechanism between the bias circuit and the oscillator core. The reset signal periodically discharges the bias circuit through a reset transistor, acting as a mediator that removes noise accumulation without requiring complex filtering or regulation circuits. This intermediary approach simplifies the overall architecture compared to traditional noise reduction methods.
2Reliability
If reset pulse timing is calibrated to zero-crossing point of the sinusoidal wave, then phase noise reduction effectiveness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The reset circuit is designed to operate without requiring external calibration or timing synchronization. The reset transistor automatically discharges the bias circuit when the oscillation signal reaches certain voltage thresholds, using the signal itself to control the reset timing. This self-service mechanism eliminates the need for precise manual calibration to zero-crossing points, reducing manufacturing precision requirements while maintaining effective phase noise reduction.
Solution Approach 2:
The invention changes the control parameter from precise timing calibration to voltage-threshold-based automatic control. Instead of requiring the reset pulse to be precisely timed to the zero-crossing point, the system uses the inherent voltage swings of the oscillation signal to automatically trigger reset events. This parameter change from time-based to voltage-based control significantly reduces manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces phase noise without complex calibration, minimizing costs and side effects, thereby improving the phase noise-related performance of the electronic system.
Implementation Method 1
providing an alternating current (AC) ground path for noise on the bias voltage
Data Source
AI summary
A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.