Oscillator Clock Shutdown Sequencing for Low-Power Wake-Up
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Solution Overview
Problem
Conventional embedded oscillator systems consume significant power due to the system clock even in low power mode, necessitating a solution to reduce power consumption while maintaining correct operation upon wake-up.
Innovation Solution
An oscillator control system with dynamic control that transitions between modes by disabling the oscillator and system clock signals after specific time periods, allowing processes to close before disabling the oscillator, and enabling synchronized wake-up without a low frequency clock source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the system clock is kept running in low power mode to enable synchronous wake-up operation, then the system can maintain correct operation upon wake-up, but power consumption remains high
Solution Approach 1:
The system performs preliminary actions by closing all processes and disabling the system clock before disabling the oscillator. This sequence ensures that when the system wakes up, all processes are ready to resume and the oscillator can be re-enabled without requiring the system clock to remain running, thus reducing power consumption while maintaining operational correctness
Solution Approach 2:
The system dynamically adjusts its operation mode by transitioning between different states: in low power mode, both the system clock and oscillator are disabled; upon wake-up, the oscillator is re-enabled first, followed by the system clock. This dynamic switching allows the system to optimize power consumption based on operational requirements
2Use of energy by moving object
If the oscillator is disabled immediately to reduce power consumption, then power savings are maximized, but the system response time to changes and commands increases
Solution Approach 1:
The system performs preliminary actions by monitoring for additional change signals during a first time period before committing to the shutdown sequence. This preliminary monitoring phase ensures that if new events occur, the system can delay or cancel the shutdown, thereby maintaining responsiveness to changes while still achieving power savings when no further events are detected
3Reliability
If a time delay is introduced before disabling the oscillator to allow processes to close, then correct operation upon wake-up is maintained, but the time to enter low power mode increases
Solution Approach 1:
The system performs preliminary actions by initiating the process closure sequence immediately upon detecting the first change signal, and simultaneously starts the time delay counter. This allows processes to begin closing while the system prepares for shutdown, overlapping the process closure time with the delay period, thus minimizing the overall time to enter low power mode while ensuring processes are closed before the oscillator is disabled
Solution Approach 2:
The system uses periodic time periods (first time period for process closure, second time period for oscillator disable) to manage the transition to low power mode. This structured periodic approach ensures that processes have adequate time to close while limiting the total delay, balancing reliability requirements with efficient power mode transition
Data Source
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AI summary
The disclosure relates to an oscillator control system with dynamic control for power saving. Example embodiments include an oscillator control system (100) comprising: an oscillator (101) configured to provide an oscillator clock signal (osc_clk) in response to receiving an oscillator enable signal (en_osc); a system clock signal generator (103) configured to generate a system clock signal (sys_clk); a system controller (104) connected to receive a system clock signal (sys_clk) from the clock signal generator (103); and an oscillator controller (102) configured to provide the oscillator enable signal (en_osc) to the oscillator (101) and receive the oscillator clock signal (osc_clk), to receive the system clock signal (sys_clk) from the clock signal generator (103) and a system mode signal (sys_mode) from the system controller (104), and to receive a first change of state signal from an input (106, 108) of the oscillator control system (100), wherein the oscillator controller (102), on receiving the first change of state signal, is configured to transition the oscillator control system (100) from a first mode in which the oscillator clock signal and system clock signal are enabled to a second mode in which the oscillator clock signal and system clock signal are disabled by disabling the system clock signal (clk_enable) after a first set time period (301) from receiving the change of state signal and to disable the oscillator enable signal (en_osc) after a second set time period (302) following the first set time period (301).