Oscillator Circuit With Split Cycle and Duty Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing oscillator circuits in semiconductor memory devices face challenges in generating an accurate clock signal due to response delays and input offset voltages of amplifiers, leading to longer cycle times than desired.
Innovation Solution
The proposed oscillator circuit includes a configuration with SR latches, cycle generating units, duty generating units, and a logic circuit, utilizing current sources, OP amplifiers, capacitors, and switches to generate clock signals with even and odd cycle times and duties, allowing independent control and reduction of input offset voltages and delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the target cycle of the generated clock signal is reduced to achieve faster operation, then the response delay of the amplifiers increases, but the accuracy of the clock signal deteriorates
Solution Approach 1:
The oscillator circuit is divided into two separate sets: a first set including a first amplifier A1 and capacitor C1 for generating the high period tH, and a second set including a second amplifier A2 and capacitor C2 for generating the low period tL. Each set independently controls one period, allowing separate optimization and compensation of response delays for each amplifier, thereby improving overall clock signal accuracy at faster cycles
Solution Approach 2:
The circuit changes the operational parameters of the amplifiers by providing separate pre-charge currents (first pre-charge current for C1, second pre-charge current for C2) and separate driving currents. This allows independent tuning of the charging and discharging rates for each capacitor, compensating for the response delays of individual amplifiers and maintaining accurate clock signal generation even at reduced cycle times
2Speed
If the target cycle of the generated clock signal is reduced to achieve faster operation, then the pre-charge time of the capacitors is reduced, but the response delay of the amplifiers increases, resulting in longer actual cycle time
Solution Approach 1:
The capacitors C1 and C2 are pre-charged to specific voltages (first pre-charge voltage for C1, second pre-charge voltage for C2) before the main oscillation cycle begins. This preliminary action ensures that the capacitors are ready to quickly respond to the oscillation triggers, reducing the overall cycle time while maintaining accurate timing despite amplifier response delays
Solution Approach 2:
The circuit dynamically adjusts the pre-charge voltages and currents for each capacitor based on the operational requirements. The first pre-charge voltage for C1 and second pre-charge voltage for C2 can be independently controlled, allowing the system to optimize the charging phase for each period, thereby reducing the actual cycle time while compensating for fixed amplifier response delays
3Device complexity
If the input offset voltage of the amplifiers is present, then the simplicity of the circuit is maintained, but the accuracy of the generated clock signal deteriorates
Solution Approach 1:
The input offset voltage issue is extracted and addressed separately for each amplifier. By having two independent amplifier sets (A1 with C1, A2 with C2), the offset voltage of each amplifier becomes an independent parameter that can be individually compensated or calibrated without affecting the other set, thereby maintaining circuit simplicity while improving clock signal accuracy
Data Source
AI summary
An oscillator circuit is provided. A first and a second cycle generating units, and a first and a second duty generating units are included. An SR latch, receiving outputs the first and second cycle generating units. In the SR latch, an output is provided to the first cycle generating unit and the third duty generating, and a contemporary output is provided to the second cycle generating unit and the second duty generating unit. A logic circuit receives the outputs of the first and the second duty generating units and the output and the contemporary output of the SR latch to generate a clock signal. The first and the second cycle generating units are respectively operated to provide the even and odd cycle times of the clock signal. The first and the second duty generating units are respectively operated to provide the even and odd duties of the clock signal.