Oscillator Synchronization Window for Intermittent Reference Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Phase-Locked Loop (PLL) devices face challenges in synchronizing with a reference signal that is not continuously available, especially when it disappears and reappears with random phase shifts, leading to phase errors and potential failure in synchronization.
Innovation Solution
An oscillator arrangement that dynamically adjusts its free-running period to match the reference signal period by incorporating a synchronization mechanism with a variable time window (T3) to capture synchronization triggers, ensuring no short semi-periods are generated and allowing for fast locking, even when the reference signal is unavailable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PLL is used to synchronize the oscillator with the reference signal, then the frequency can be adjusted to match the reference signal phase, but the synchronization fails when the reference signal disappears and reappears with random phase shifts
Solution Approach 1:
The patent applies preliminary action by defining a capture range window (T3) before the reference signal appears, during which the oscillator is prepared to accept synchronization triggers. When the reference signal reappears, the system can immediately capture it within this pre-established window, enabling fast locking without requiring continuous reference signal presence. This resolves the contradiction by preparing the system in advance for intermittent signal conditions.
Solution Approach 2:
The patent implements dynamics by making the half-cycle duration variable through dynamic adjustment of the capture range window T3. The synchronizer can prolong the second part of the half-cycle to extend T3, allowing the system to adapt its time characteristics in real-time based on whether synchronization triggers are detected. This dynamic behavior enables the oscillator to handle both continuous and intermittent reference signals effectively.
2Productivity
If the oscillator uses a fixed free-running period, then the design is simple, but it cannot quickly synchronize when the reference signal reappears after disappearance
Solution Approach 1:
The system performs preliminary action by pre-defining the capture range window T3 and preparing the synchronizer to detect triggers within this window before the reference signal actually appears. This preparation enables immediate synchronization upon signal reappearance, achieving fast locking (high productivity) without requiring complex real-time adjustment mechanisms during the critical capture phase.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the duration of the capture range window T3 based on synchronization needs. The controller can prolong the second part of the half-cycle to increase T3 when fast locking is required, and reduce it during steady-state operation. This selective parameter adjustment achieves high synchronization speed when needed while maintaining simpler operation during normal conditions, balancing productivity and complexity.
3Measurement precision
If the oscillator synchronizes to every reference signal edge, then synchronization accuracy is high, but short semi-periods are generated causing glitches
Solution Approach 1:
The patent applies segmentation by dividing the half-cycle into distinct parts: a first part with fixed duration and a second part that can be prolonged to extend the capture range window T3. This segmentation allows the system to accept synchronization triggers only during the extended second part, ensuring adequate semi-period duration while maintaining synchronization accuracy. Triggers occurring during the first part are rejected, preventing short semi-period generation and associated glitches.
Solution Approach 2:
The system performs preliminary action by pre-establishing the capture range window T3 within the half-cycle structure before synchronization triggers occur. By defining where triggers should be captured (during the second part of the half-cycle) and where they should be rejected (during the first part), the system ensures that accepted triggers will not produce short semi-periods, thereby eliminating glitches while maintaining synchronization precision.
Data Source
AI summary
An oscillator arrangement having an oscillator configured to generate an oscillation signal having two half-cycles, an input configured to receive a synchronization signal including synchronization triggers, a synchronizer configured to reject a synchronization trigger received during a first part of a half-cycle and to synchronize the oscillator to a synchronization trigger received during a second part of the half-cycle, and a controller configured to prolong the second part of the half-cycle in response to receiving a synchronization trigger during the first part of the half-cycle.