Oscillator Circuit Synchronization Reduces Pin Count

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Solution Overview

Problem

Existing power supply controllers require multiple signal inputs for synchronization, leading to increased pin count in semiconductor packages, higher costs, and power dissipation due to large capacitive loads.

Innovation Solution

A power supply controller design that synchronizes with externally received frequencies using a single package pin, featuring an oscillator circuit with a control circuit and timing element, allowing synchronization without jitter and reducing pin count and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple signal inputs are used for oscillator synchronization, then synchronization reliability is improved, but pin count and package cost increase

Engineering Contradiction:

Improvesynchronization reliabilityVSAvoidpin count

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple synchronization signal inputs into a single pin by implementing an internal multiplexer or selector circuit that chooses between different synchronization sources (external oscillator signal, internal oscillator, or other controllers) through a single package pin, thereby reducing pin count while maintaining synchronization reliability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The single synchronization pin is designed to handle multiple functions: receiving external oscillator signals, accepting synchronization from other controllers, and potentially providing feedback signals, replacing what would traditionally require multiple dedicated pins

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple capacitors are driven for synchronization, then synchronization capability is improved, but power dissipation increases

Engineering Contradiction:

Improvesynchronization capabilityVSAvoidpower dissipation

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements periodic synchronization signal transmission instead of continuous driving of multiple capacitors, using pulse-based or intermittent synchronization updates that maintain synchronization capability while significantly reducing average power consumption

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent extracts or removes the need for multiple capacitive load drivers by implementing a high-impedance output stage that can drive a single capacitor or minimal capacitive load, eliminating the requirement to drive large capacitive loads while maintaining synchronization function

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If multiple capacitors are driven for synchronization, then synchronization capability is improved, but synchronization delay increases

Engineering Contradiction:

Improvesynchronization capabilityVSAvoidsynchronization delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent removes the bottleneck of driving multiple large capacitors by designing an output stage that drives a single small capacitor or uses a buffer architecture, thereby extracting the time delay caused by large capacitive loads and achieving faster synchronization response

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS7800456B2Method of forming an oscillator circuit and structure therefor

Publication Date: 2010.09.21 SEMICON COMPONENTS IND LLC

AI summary

In one embodiment, an oscillator circuit is configured to oscillate at a base frequency. The oscillator is configured to receive a synchronization signal and restart a period of the oscillator signal responsively to the synchronization signal.