Oscillator TDC Calibration for Constant Time Resolution
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) face challenges in achieving high time resolution while adapting to a wide frequency range, as their time resolution becomes non-constant due to variations in manufacturing process, power supply voltage, and temperature, leading to the need for complex corrections or redundant elements.
Innovation Solution
The implementation of an all-digital phase-locked loop (ADPLL) with a digitally-controlled coupled oscillator, a vernier time-to-digital converter, and a digital control unit that adjusts the current value supplied to the coupled oscillator using a current mirror circuit, allowing for calibration of phase differences between clock outputs to maintain constant time resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a TDC uses element delay amounts for time measurement, then high time resolution is achieved, but the time resolution becomes non-constant due to PVT variations
Solution Approach 1:
The patent implements a feedback mechanism where the TDC measures its own delay element variations using a phase detector that compares the original clock signal with delayed versions of itself. The measured phase differences are used to generate correction values that compensate for PVT-induced delay variations, thereby maintaining constant time resolution across different operating conditions.
Solution Approach 2:
The patent changes the operational parameters of delay elements dynamically by applying correction values derived from real-time phase measurements. These parameter adjustments compensate for environmental variations, allowing the TDC to maintain high and constant time resolution despite changes in manufacturing process, voltage, or temperature.
2Stability of the object's composition
If correction mechanisms are added to maintain constant time resolution, then time resolution stability is improved, but device complexity increases
Solution Approach 1:
The patent designs the phase detector and correction mechanism to serve multiple functions: it not only measures phase differences for time resolution calibration but also provides feedback for ongoing compensation during operation. This multi-functionality reduces the need for separate correction circuits, thereby limiting the increase in device complexity.
Solution Approach 2:
The TDC system performs self-calibration and self-correction by using its own internal signals to detect and compensate for delay variations. The phase detector uses the TDC's own clock outputs to measure delays, and the correction mechanism automatically adjusts based on these measurements, eliminating the need for external calibration equipment or complex control systems.
3Reliability
If redundant delay elements are prepared to ensure time resolution, then time resolution reliability is improved, but circuit scale increases
Solution Approach 1:
The patent replaces the mechanical approach of using redundant physical delay elements with an electronic/software-based correction system. Instead of duplicating delay elements to ensure reliability, the system uses measured phase information to computationally compensate for variations, significantly reducing the circuit area while maintaining or improving reliability.
Data Source
AI summary
An object is to provide a method for preventing the occurrence of variations in time resolution by providing a calibration process to a TDC at the time of start up and further preventing the increase in circuit scale by reducing the redundancy of delay elements. A calibration of a multiphase oscillator TDC and a vernier TDC is carried out at the time of power-on. In the calibration, a timing input to be input to the vernier TDC is selected from output signals of DCCO based on a reference clock. Also, data is defined as an output signal which is adjacent to the output signal of DCCO mentioned above and proceeds in phase, and the delay therebetween is derived. By repeating it to all of the output signals, the one cycle of the output signal of DCCO is derived.