Differential Oscillator Terminal Layout for Low-Jitter Clock Output

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Solution Overview

Problem

Existing oscillators with diagonal placement of power supply and ground terminals suffer from impaired decoupling capacitor effectiveness due to parasitic inductance from through-hole connections, leading to increased power supply noise and jitter in clock signals.

Innovation Solution

The power supply and ground terminals are arranged side by side, along with the positive and negative clock terminals, minimizing parasitic inductance and allowing for direct coupling of capacitors without vias, thereby enhancing signal quality and reducing noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the power supply terminal and ground terminal are arranged at diagonal positions in the package, then the layout follows conventional six-terminal oscillator design, but the decoupling capacitor effect is impaired due to parasitic inductance of through holes

Engineering Contradiction:

Improveconventional layout designVSAvoiddecoupling capacitor effect

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent inverts the conventional diagonal arrangement of power supply and ground terminals to a side-by-side arrangement. This inversion eliminates the need for through-hole connections, thereby removing the parasitic inductance that impaired the decoupling capacitor effect in traditional designs.

Inventive Principle:

Principle #13The other way round (Inversion)

2Ease of operation

If through holes are used for connecting wiring in the mounting board, then the power supply and ground terminals can be connected, but parasitic inductance increases and impairs decoupling capacitor effectiveness

Engineering Contradiction:

Improveterminal connectionVSAvoidparasitic inductance

Core Design Contradiction:

Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and eliminates the through-hole connection structure from the mounting board design. By removing the through holes, the parasitic inductance inherent in such connections is eliminated, allowing the decoupling capacitor to function effectively without the harmful inductive effects.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If the power supply terminal and ground terminal are arranged side by side, then parasitic inductance is minimized and decoupling capacitor effect is maximized, but the layout deviates from conventional diagonal arrangement

Engineering Contradiction:

Improvenoise rejectionVSAvoidlayout configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by optimizing the terminal arrangement specifically for noise reduction purposes. The power supply and ground terminals are positioned side by side in a localized area to minimize the loop area and parasitic inductance, while other parts of the oscillator maintain conventional design characteristics.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS12519424B2Oscillator and electronic apparatus

Publication Date: 2026.01.06 SEIKO EPSON CORP

AI summary

An oscillator includes a power supply terminal, a ground terminal, a positive-side clock terminal, and a negative-side clock terminal. The power supply terminal is supplied with a high potential-side power supply voltage. The ground terminal is supplied with a low potential-side power supply voltage. The positive-side clock terminal outputs a positive-side clock signal of a differential clock signal. The negative-side clock terminal outputs a negative-side clock signal of the differential clock signal. The power supply terminal and the ground terminal are arranged side by side, and the positive-side clock terminal and the negative-side clock terminal are arranged side by side.