Oscillator Voltage and Code Scaling for Target Frequency Tracking
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Solution Overview
Problem
Conventional dynamic voltage and frequency scaling (DVFS) techniques do not adequately address changes in physical parameters and characteristics of processor chips due to variations in fabrication and aging, leading to inefficiencies in power management and potential hardware damage.
Innovation Solution
An adaptive voltage and code scaling (DVCS) mechanism that uses a frequency-locked loop (FLL) controller to monitor physical parameter changes and feed back to a DVCS controller for real-time voltage correction, enabling fine adjustments to operating voltage and frequency to match target computing power while optimizing energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If operating voltage is increased to maintain processor stability at higher frequencies, then processor reliability is improved, but power consumption and heat generation increase significantly
Solution Approach 1:
The patent implements dynamic voltage scaling by continuously monitoring oscillator frequency and adjusting voltage in real-time based on actual processor needs rather than using static voltage-frequency curves. The DVCS controller dynamically modifies voltage levels to match actual operating conditions, allowing the system to use lower voltages when full performance is not required while maintaining stability when needed.
Solution Approach 2:
The system employs a feedback mechanism where the DVCS controller monitors oscillator frequency output and uses this information to adjust voltage levels. The frequency-locked loop controller provides continuous feedback about actual frequency operation, enabling the system to adapt voltage dynamically rather than relying on pre-defined voltage-frequency relationships, thus optimizing power consumption while maintaining reliability.
2Reliability
If conventional DVFS techniques use large voltage margin to ensure proper processor operations, then processor reliability is improved, but energy efficiency deteriorates
Solution Approach 1:
The patent replaces static voltage-frequency curves with dynamic voltage scaling that adapts to actual operating conditions. The system continuously monitors oscillator frequency and adjusts voltage margins based on real-time feedback, eliminating the need for large fixed voltage margins while maintaining processor reliability. This dynamic approach reduces energy waste associated with excessive voltage headroom.
Solution Approach 2:
The system changes the operating voltage parameter dynamically based on monitored frequency conditions rather than maintaining a fixed voltage margin. The DVCS controller adjusts voltage levels in response to actual frequency operation, allowing the voltage parameter to adapt to changing conditions and eliminating the energy inefficiency of fixed large voltage margins.
3Productivity
If operating frequency is increased to meet heavy workload demands, then processor productivity is improved, but operating voltage must be increased causing heat generation
Solution Approach 1:
The patent implements dynamic voltage scaling that adjusts voltage levels in real-time based on actual frequency operation and workload conditions. Rather than maintaining high voltage to support peak frequency indefinitely, the system dynamically scales voltage to match actual performance needs, reducing heat generation during sustained lower-intensity operations while maintaining the ability to achieve high productivity when required.
Data Source
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AI summary
A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop, FLL, (610). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit, PMU, to cause the PMU to supply an adjusted operating voltage to the FLL (620). The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature (630). The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.