Oscillator Supply-Voltage Feedback for Clock Frequency Stability

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Solution Overview

Problem

Electronic devices face challenges in maintaining frequency stability of clock signals due to changes in operating conditions, which can lead to frequency shifts and reduced accuracy, especially when multiple clients with different loading conditions are enabled or disabled, affecting communication quality.

Innovation Solution

A clock generator with an oscillator circuit and a frequency stabilization circuit coupled to the same supply voltage, where the stabilization circuit adjusts the average supply voltage to compensate for frequency shifts caused by loading conditions, achieving fine frequency-tuning resolution without increasing size or power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the clock generator provides clock signals to multiple clients with different loading conditions, then the adaptability of the system is improved, but the frequency stability deteriorates due to frequency shifts caused by varying load conditions

Engineering Contradiction:
Improveability to serve multiple clientsVSAvoidfrequency stability
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The frequency stabilization circuit continuously monitors the supply voltage and adjusts it in real-time to compensate for frequency shifts. The circuit draws power from the supply voltage in a feedback-controlled manner, changing the supply voltage by a small amount over a discontinuous sequence of time intervals to maintain stable oscillator frequency despite varying load conditions

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The frequency stabilization circuit dynamically changes the supply voltage parameter to compensate for frequency shifts. By adjusting the supply voltage to the oscillator circuit, the circuit achieves fine frequency-tuning resolution on the order of one or more parts per billion (ppb) while accommodating different loading conditions

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If frequency stabilization is implemented to achieve fine frequency-tuning resolution, then the frequency accuracy is improved, but the device complexity increases

Engineering Contradiction:
Improvefrequency accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The frequency stabilization circuit is designed to perform multiple functions: it stabilizes the supply voltage, compensates for frequency shifts, and accommodates varying load conditions. This multi-functional approach achieves fine frequency-tuning resolution without requiring separate dedicated circuits for each function, thereby limiting the increase in device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Stability of the object's composition

If the frequency stabilization circuit operates to compensate for frequency shifts, then the frequency stability is improved, but the power consumption increases

Engineering Contradiction:
Improvefrequency stabilityVSAvoidpower consumption
Core Design Contradiction:
Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The frequency stabilization circuit draws power from the supply voltage over a discontinuous sequence of time intervals rather than continuously. This periodic operation mode allows the circuit to adjust the supply voltage to compensate for frequency shifts while minimizing overall power consumption compared to continuous operation

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11496138B2Frequency stabilization
Publication Date: 2022.11.08 QUALCOMM INC
  • US11496138B2 patent drawing
  • US11496138B2 patent drawing
  • US11496138B2 patent drawing

AI summary

An apparatus is disclosed for providing frequency stabilization. The apparatus includes a first supply voltage node, a second supply voltage node, an oscillator circuit coupled to the first supply voltage node, at least one clock buffer coupled to the second supply voltage node and an output of the oscillator circuit, and at least one load circuit. The at least one clock buffer is configured to selectively be in a disabled state or an enabled state to pass the clock signal to at least one client of multiple clients. The at least one load circuit includes an input coupled to the output of the oscillator circuit. The at least one load circuit also includes an output configured to be coupled to a ground. The at least one load circuit is configured to be connected to the first supply voltage node for at least a portion of time.