Variable Size Load Unit Cache Management via OTC
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Solution Overview
Problem
Existing memory systems in embedded information systems, such as in-vehicle environments, face challenges in managing variable-sized load units efficiently, leading to issues like fragmentation and inefficient memory use due to the limitations of traditional cache management strategies, which can impact real-time processing requirements.
Innovation Solution
The implementation of an Operating System Aware Task Caching (OTC) system that decouples load request and eviction operations, allowing for the management of variable-sized load units by identifying and optimizing eviction candidates in advance, thereby optimizing cache behavior and reducing internal memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional cache management strategies are used, then cache operations are simple, but memory fragmentation occurs and memory use efficiency deteriorates
Solution Approach 1:
The patent segments the cache into multiple ways (e.g., 4 ways) where each way can independently store load units of different sizes. This segmentation allows the cache to efficiently accommodate variable-sized load units without fragmentation, as each way can be independently allocated to different tasks or applications, thereby improving memory use efficiency while maintaining manageable cache operations through structured organization.
Solution Approach 2:
The patent implements dynamic cache management where the cache allocation is not fixed but can be adjusted based on runtime conditions. The cache controller dynamically selects which ways to use and how to allocate space within ways based on the size and priority of incoming load units, allowing the system to adapt to varying memory requirements and prevent fragmentation while maintaining operational simplicity through automated dynamic allocation.
2Adaptability or versatility
If variable-sized load units are managed, then memory flexibility improves, but cache management complexity increases
Solution Approach 1:
The patent employs preliminary action by pre-organizing the cache into multiple ways with defined characteristics before runtime. The cache controller is pre-configured with the ability to handle variable-sized load units, and the cache structure is pre-established with multiple independent ways. This preliminary organization allows the cache to flexibly accommodate different load unit sizes without requiring complex runtime reconfiguration, thereby maintaining manageable complexity while achieving high adaptability.
Solution Approach 2:
The patent introduces a cache controller as an intermediary between the variable-sized load units and the cache structure. This controller mediates the allocation process by automatically selecting appropriate cache ways and managing load unit placement, thereby shielding the variable-sized load unit management from directly increasing system complexity. The intermediary handles the complexity of variable size management internally while presenting a simplified interface to the rest of the system.
3Volume of stationary object
If internal memory size is reduced, then cost decreases, but access speed to external memory deteriorates
Solution Approach 1:
The patent applies the nested doll principle by creating a hierarchical memory structure where the cache is nested within the memory hierarchy, with multiple levels of caching. The cache controller manages this nested structure to provide fast access to frequently used load units in the cache while offloading less frequently accessed data to external memory. This nested arrangement allows the system to use smaller internal memory while maintaining fast access speeds through intelligent caching at multiple levels.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting cache allocation parameters based on access patterns and load unit characteristics. The cache controller monitors and adjusts parameters such as cache way selection, load unit size allocation, and replacement policies to optimize the balance between internal memory usage and external memory access speed. By changing these parameters dynamically, the system achieves fast external memory access despite reduced internal memory size.
Data Source
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AI summary
Systems and methods of managing variable size load units of application codes in a processing system include identifying pages of a random access memory (RAM) device to store copies of load units from an external memory device upon request by a bus master in the processing system. The RAM device is internal to an integrated circuit device that includes the bus masters, and the external memory device is external to the integrated circuit device. The bus masters execute the application codes, and each of the application codes comprise one or more load units that include executable program instructions. At least some of the load units have different sizes from one another. A page type indicator is determined for an identified page. A first page type indicates whether the identified page is a split page to store a segment of each of two different load units.