OTN Clock Transient Suppression via Nested ODU Wrapping

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Solution Overview

Problem

Optical Transport Networks (OTNs) experience clock transients and frame slips during switching, leading to unavailable control plane signaling and user service disruptions, with conventional solutions only mitigating issues rather than eliminating them.

Innovation Solution

Implementing a 'double wrapper' configuration where an Optical channel Data Unit (ODU) signal is transmitted within an overclocked OTN signal, using Generic Mapping Protocol (GMP) or variants, to insulate control plane signaling and Operations, Administration, Maintenance, and Provisioning (OAM&P) data from clock transients and framing events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional single-wrapper OTN configuration is used, then device complexity is reduced, but control plane signaling and OAM&P operations are disrupted by clock transients during switching

Engineering Contradiction:
Improvecontrol plane signaling continuityVSAvoiddouble wrapper configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent embeds an inner ODU signal carrying control plane signaling and OAM&P data within an outer ODU signal that carries user data. This nested structure allows the inner signal to be insulated from clock transients affecting the outer signal during switching operations, maintaining control plane continuity while transporting user traffic.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The inner ODU signal acts as an intermediary carrier for control plane signaling, separated from the outer ODU signal that is subject to clock transients. This mediation through nested structures protects critical control data from timing disruptions while maintaining overall system functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If ODU signal switching is performed, then network adaptability is improved, but clock transients cause frame slips and service disruptions

Engineering Contradiction:
Improveswitching capabilityVSAvoidframe alignment stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the OTN signal into distinct inner and outer ODU signals with separate timing domains. The inner signal carrying control data is segmented from the outer user data signal, allowing independent timing management that prevents frame slips from propagating to critical control plane operations during switching events.

Inventive Principle:
Principle #1Segmentation

3Object-affected harmful factors

If alarm hold-off and conditioning are used, then harmful alarm effects are mitigated, but control plane signaling remains unavailable during transient recovery

Engineering Contradiction:
Improvespurious alarm suppressionVSAvoidcontrol plane unavailability duration
Core Design Contradiction:
Object-affected harmful factorsVSLoss of time

Solution Approach 1:

The nested inner ODU signal serves as a protected intermediary channel that maintains control plane signaling availability even when the outer user data signal experiences clock transients. This eliminates the control plane unavailability period by providing a separate, insulated timing domain for critical signaling.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9264139B2Optical transport network clock transient suppression systems and methods
Publication Date: 2016.02.16 CIENA CORP
  • US9264139B2 patent drawing
  • US9264139B2 patent drawing
  • US9264139B2 patent drawing

AI summary

An Optical Transport Network (OTN) method, an OTN switching node method, and an OTN node utilize a “double wrapper” configuration to eliminate clock transients in OTN networks. That is, the systems and methods bury an ODU beneath another overclocked ODU thereby eliminating any interruptions due to clock transients, framing events or other disruptions. For example, an ODU2 can be mapped into an ODU2e, an ODU3 can be mapped into an ODU3e2, an ODU4 can be mapped into an ODUG or some other overclocked variant of ODU4, and the like. Specifically, ODU2e, ODU3e2, ODUG, etc. are overclocked variants of ODU2, ODU3, ODU4, etc. The systems and methods propose to use these overclocked signals to carry standard ODU signals to eliminate clock transient problems.