OTN FEC Mapping with BCH Parity for Higher Error Rates

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Solution Overview

Problem

Current forward error correction (FEC) techniques in optical transport networks (OTN) do not provide sufficient protection against bit errors, especially in systems that introduce higher error rates, without altering the line rate or frame structure.

Innovation Solution

The implementation of an encoder and decoder system that uses Bose, Chaudhuri, and Hocquenghem (BCH) or Reed Solomon (RS) encoding techniques to insert and process column and row parity information within OTN frames, providing stronger FEC protection while maintaining the original frame structure and line rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If current FEC techniques are used, then the implementation is simple, but the error correction capability is insufficient for high error rate systems

Engineering Contradiction:
Improveerror correction capabilityVSAvoidFEC implementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the FEC implementation into distinct functional modules: a mapping module that transforms Reed-Solomon encoded data into BCH encoded format, and a processing module that handles the segmented BCH encoding. This segmentation allows the system to achieve superior error correction capability through BCH codes while maintaining manageable complexity through modular design. The mapping module specifically converts data from one encoding structure to another, enabling the receiver to use more powerful BCH decoding algorithms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the encoding parameters by transitioning from standard Reed-Solomon FEC to BCH FEC with specific parameters (e.g., (255, 223) BCH codes). This parameter change enables stronger error correction capability suitable for high error rate systems. The mapping module implements this parameter change by transforming the data structure to match the new BCH encoding parameters, thereby improving reliability without requiring a complete system redesign.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If stronger FEC protection is implemented, then error correction capability improves, but the frame structure and line rate must be altered

Engineering Contradiction:
ImproveFEC protection strengthVSAvoidframe structure compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements a universal mapping module that can handle multiple encoding formats and parameters while maintaining compatibility with the existing OTN frame structure. This mapping module serves multiple functions: it transforms Reed-Solomon encoded data to BCH encoded format, adapts to different code parameters, and preserves the original frame structure. This multi-functionality allows the system to provide stronger FEC protection through BCH codes without altering the line rate or frame structure, ensuring compatibility with existing network infrastructure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The mapping module acts as an intermediary between the existing OTN frame structure and the new BCH FEC encoding scheme. It receives data in the original format, performs the necessary transformations to enable BCH encoding, and outputs data that maintains compatibility with the existing frame structure. This intermediary approach allows the implementation of stronger FEC protection while preserving frame structure compatibility, as the mapping module bridges the gap between the two encoding paradigms without requiring changes to either the input or output formats.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If BCH or RS encoding with parity information is added, then FEC protection improves, but processing complexity increases

Engineering Contradiction:
ImproveFEC encoding protectionVSAvoidencoding and decoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-calculating and pre-organizing the parity information structure during the mapping phase. The mapping module prepares the data in a format optimized for BCH encoding, pre-establishing the relationship between data bits and parity bits. This preliminary preparation simplifies the subsequent encoding and decoding operations, as the structure is already optimized for BCH processing. The receiver can then efficiently process the pre-organized parity information without dealing with the complexity of structure establishment during real-time decoding.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a new dimension to the FEC processing by implementing a mapping layer that transforms the data representation from Reed-Solomon format to BCH format. This dimensional transformation adds a new processing layer that organizes parity information in a way that exploits the mathematical properties of BCH codes. By changing the dimensional organization of the code structure, the system achieves stronger error correction capability while the structured approach to this transformation keeps the processing complexity manageable through systematic methodology.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7415658B2Forward error correction mapping and de-mapping techniques
Publication Date: 2008.08.19 INTEL CORP
  • US7415658B2 patent drawing
  • US7415658B2 patent drawing
  • US7415658B2 patent drawing

AI summary

Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.