OTN Transponder NJO PJO Mapping 10 GbE Signals
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Solution Overview
Problem
Current Optical Transport Network (OTN) systems lack support for 100% bit transparent 10 Gb/s Ethernet LAN-PHY transport methods, leading to complexities in clock generation and de-multiplexing, and are unable to efficiently multiplex 100% transparent OTU2-LAN rate signals, which are preferred by network operators for long-haul transport.
Innovation Solution
The introduction of Negative Justification Opportunities (NJO) and Positive Justification Opportunities (PJO) in unused OPUk overhead and payload areas, respectively, allows for wider clock tolerance signals to be mapped and multiplexed asynchronously into OTU2-LAN and OTU3-LAN rate transport signals, providing additional bandwidth for client data rate offsets beyond standard OTN specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous mapping method (CBRx-a) is used to provide ±20 PPM payload tolerance, then clock tolerance is improved, but the system cannot support 100% bit transparent transport and ±100 PPM clock tolerance signals
Solution Approach 1:
The patent segments the OPUk frame structure by adding separate NJO and PJO bytes in addition to the existing JC bytes. This segmentation allows independent control of negative and positive justification opportunities, enabling the system to handle wider clock tolerances (±100 PPM) while maintaining 100% bit transparent transport capability. The segmentation of justification mechanisms resolves the contradiction by providing dedicated fields for each type of rate adjustment.
Solution Approach 2:
The patent extends the existing one-dimensional justification control (JC bytes) by adding another dimension through NJO and PJO bytes. This dimensional expansion allows the system to simultaneously support multiple clock tolerance requirements and transparent transport modes that were previously incompatible, resolving the contradiction between clock tolerance and transport transparency.
2Adaptability or versatility
If synchronous mapping (CBRx-b) is used to achieve 100% bit transparent transport, then transparency is improved, but the system requires higher than standard OTU2 bit rate and complex clock generation
Solution Approach 1:
The patent introduces NJO and PJO bytes as intermediary elements between the client signal and the OTUk transport signal. These intermediary justification bytes absorb the clock rate differences and allow synchronous mapping to achieve 100% bit transparency without requiring complex clock generation circuits. The NJO/PJO mechanism mediates the rate adaptation, simplifying the clock generation requirements.
3Adaptability or versatility
If standard OPUk frame structure is used, then compliance with ITU-T G.709 is maintained, but additional bandwidth for client data rate offsets beyond ±20 PPM is not available
Solution Approach 1:
The patent enhances the universality of the OPUk frame structure by making it multi-functional. The added NJO and PJO bytes serve multiple purposes: they provide additional bandwidth for client data rate offsets, maintain compatibility with existing ITU-T G.709 structures, and enable support for both synchronous and asynchronous mapping methods. This multi-functionality resolves the contradiction between maintaining standard compliance and providing extended capability.
4Reliability
If asynchronous multiplexing (ODU[i]j) is used to provide ±20 PPM per tributary, then clock tolerance is improved, but the system cannot handle ±100 PPM client offset with sufficient buffer
Solution Approach 1:
The patent applies preliminary action by pre-configuring additional NJO and PJO bytes in the OPUk frame structure before multiplexing occurs. This preliminary allocation of justification bytes provides the necessary buffer capacity to handle short-term large offset changes and ±100 PPM client variations, resolving the contradiction between clock tolerance and buffer capacity for short-term variations.
Data Source
AI summary
The present invention provides systems and methods for mapping and multiplexing wider clock tolerance signals in Optical Transport Network (OTN) transponders and multiplexers. In one exemplary embodiment, the present invention allows wide tolerance signals, such as a 10 GbE with a ±100 PPM clock tolerance, to be 100% transparently mapped asynchronously into OTU2-LAN rate transport signals. In another exemplary embodiment, the present invention allows wide tolerance signals, such as a 10 GbE with a ±100 PPM clock tolerance, to be 100% transparently multiplexed asynchronously in to OTU3-LAN rate transport signals. The present invention utilizes extra Negative Justification Opportunities (NJO) in either unused OPUk overhead or in OPUk payload area and Positive Justification Opportunities (PJO) in OPUk payload area. Advantageously, the extra NJO and PJO provide additional bandwidth for client data rate offsets beyond OTN specifications.