OTN Packet Delay Control via Phase Locked Loop
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Solution Overview
Problem
Current optical transport networks (OTN) experience variable and non-deterministic delays, which hinder the efficient transport of Ethernet packets and Time of Day (ToD) synchronization, leading to performance degradation in network timing protocols like NTP and IEEE1588.
Innovation Solution
A method and apparatus that measure and control delays in the data path to establish a fixed latency, using a phase locked loop to adjust the outgoing clock signal and ensure deterministic delay, allowing for reliable transport of Ethernet packets and synchronization signals over OTN networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Ethernet packets are transported over OTN network, then cost-efficient transport is achieved, but variable delays occur causing non-deterministic packet transport
Solution Approach 1:
The system performs preliminary delay measurement during a measurement period before actual packet transport. The average delay is calculated in advance and stored as configuration data, enabling deterministic delay control without requiring continuous real-time measurement during normal operation.
Solution Approach 2:
The system uses feedback from delay measurements to adjust the outgoing clock signal phase through a phase locked loop. The measured average delay is fed back to control the clock phase, creating a closed-loop system that compensates for OTN network delays and achieves deterministic packet transport timing.
2Measurement precision
If IEEE1588 transparent clock function is implemented, then ToD synchronization is improved, but layer 1 synchronization is broken
Solution Approach 1:
The patent introduces an intermediary approach by measuring and compensating for delays at the clock signal level before packet transmission. The phase adjustment of the outgoing clock signal acts as a mediator that pre-compensates for OTN delays, enabling ToD synchronization without requiring IEEE1588 transparent clock functionality that would break layer 1 synchronization.
3Ease of operation
If NTP or IEEE1588 protocols are used via Ethernet packets over OTN, then network timing is achieved, but variable delays degrade performance
Solution Approach 1:
The system performs preliminary delay measurement and calculation of average delay before packet transmission. This advance characterization of the OTN path allows NTP and IEEE1588 protocols to operate with accurate timing information, compensating for variable delays and maintaining timing precision.
Solution Approach 2:
The system changes the timing parameter by adjusting the outgoing clock signal phase based on measured delays. This parameter adjustment transforms the variable delay characteristic of OTN into a compensatable effect, enabling accurate timing protocol operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in fixed latency and improved ToD synchronization performance, limiting packet delay variation to within ±50 nanoseconds, enabling efficient transport of Ethernet packets, including SyncE and NTP/IEEE1588 packets, without breaking layer 1 synchronization.
Implementation Method 1
a phase adjustment amount is determined based on the one or more measured delays over the data path in the predetermined measurement period, and based on the determining phase adjustment amount, a phase of the outgoing clock signal is adjusted by a phase locked loop
Data Source
AI summary
A method and apparatus for controlling delay over a data path in a device for transporting Ethernet packets over an optical transport network. The device is configured to receive an incoming clock signal having a first frequency and an incoming data signal and to output an outgoing clock signal having a second frequency and an outgoing data signal. One or more delays over the data path in the device are measured in a predetermined measurement period. A phase adjustment amount is determined based on the one or more measured delays over the data path in the predetermined measurement period, and based on the determining phase adjustment amount, a phase of the outgoing clock signal is adjusted by a phase locked loop in such a way that the delay over the data path in the device is substantially equal to a fixed delay value.