OTN Frame Padding and RSFEC Coding for High-Rate Transmission
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Solution Overview
Problem
Existing OTN interface designs face challenges in meeting error correction requirements for high-rate transmission and suffer from complex clock synchronization issues due to the limitations of generic forward error correction (GFEC) and staircase forward error correction (FEC) codes, particularly in intra-board interconnection scenarios.
Innovation Solution
The implementation of high-performance FEC codes such as Reed-Solomon FEC (RSFEC) or interleaved cyclic FEC, combined with clock simplified padding data, to enhance error correction performance and simplify clock design in optical transmission systems, ensuring reliable transmission and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GFEC code is used for error correction in OTN interface, then transmission reliability is improved, but error correction performance cannot meet requirements for high-rate transmission
Solution Approach 1:
The patent changes the error correction coding scheme from GFEC to RSFEC with different code parameters (e.g., RS(514,478)). This parameter change enables the system to achieve both high transmission reliability and sufficient error correction performance for high-rate transmission by selecting code parameters that provide adequate correction capability while maintaining system compatibility
2Reliability
If staircase FEC is used for encoding and decoding in optical transmission, then error correction capability is improved, but clock synchronization complexity increases
Solution Approach 1:
The patent extracts the clock synchronization function from the error correction process by using RSFEC encoding/decoding that operates independently of clock recovery. This separation allows the error correction capability to be improved through better coding while the clock synchronization is handled by dedicated mechanisms, thereby reducing overall system complexity
Solution Approach 2:
The patent introduces RSFEC as an intermediary error correction mechanism that operates between the physical layer and higher layers. This intermediary provides robust error correction without requiring complex clock synchronization between the intra-board interconnection interface and optical port, as RSFEC can operate with simpler timing requirements
Data Source
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AI summary
This application discloses a data processing method and a related apparatus. The method includes: obtaining a first data block, where the first data block is a data block obtained by dividing first optical path data; padding clock simplified padding data and the first data block into a target information bit in a first data frame to form target data, where the target information bit is an information bit that is preset in the first data frame and that is used to pad optical path data; encoding the target data by using a first error correction encoding scheme, to obtain a first code block that has a mapping relationship with the first data frame, where the first error correction encoding scheme matches a frame structure of the first data frame; and sending the first code block. According to the solutions of this application, error correction performance can be improved, and a clock design can be simplified.