OTN Frame Padding and RSFEC Encoding for High-Rate Transmission
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Solution Overview
Problem
Existing optical transport network (OTN) intra-domain interfaces face challenges in maintaining reliable transmission error correction performance as transmission rates increase, and staircase forward error correction (FEC) causes complex clock synchronization issues.
Innovation Solution
A data processing method that involves padding clock simplified padding data into a target information bit within a data frame, using error correction encoding schemes like Reed-Solomon forward error correction (RSFEC) to match the frame structure, thereby simplifying the clock design and improving error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If staircase FEC is used to perform encoding and decoding in optical transmission, then error correction performance is improved, but clock synchronization complexity increases
Solution Approach 1:
The patent extracts the clock synchronization function from the data transmission path by using a separate reference clock signal. The encoding and decoding operations use this extracted reference clock independently, separating the timing function from the data stream and thereby reducing clock synchronization complexity while maintaining error correction performance.
Solution Approach 2:
The patent changes the clock parameter from dynamic synchronization to fixed reference frequency. By using a predetermined reference clock signal with stable frequency for both encoding and decoding operations, the system eliminates the need for complex clock synchronization mechanisms while preserving the error correction capabilities of staircase FEC.
2Length of moving object
If GFEC error correction coding is used, then transmission distance is extended, but error correction performance becomes insufficient for high transmission rates
Solution Approach 1:
The patent employs a composite error correction approach by combining GFEC coding for basic error protection with additional encoding operations using a predetermined reference clock. This composite structure integrates the distance-extending capability of GFEC with the enhanced error correction performance needed for high transmission rates, achieving both goals simultaneously.
3Productivity
If transmission rate of intra-board interconnection is increased, then transmission capacity is improved, but error correction performance cannot meet reliable transmission requirement
Solution Approach 1:
The patent performs preliminary error correction encoding using a predetermined reference clock before data transmission. By pre-encoding the data with error correction codes generated from the stable reference clock, the system prepares the data to withstand high transmission rates, ensuring reliable transmission is achieved even as transmission capacity increases.
Data Source
AI summary
The present disclosure relates to data processing methods and apparatus. One example method includes obtaining a first data block from first optical path data, adding padding data and the first data block into a target information bit in a first data frame to form target data, encoding the target data to obtain a first code block, and sending the first code block.