OTP Antifuse Memory Structure for Reliable Dielectric Breakdown
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Solution Overview
Problem
Existing one-time-programmable (OTP) memory devices face challenges in achieving efficient and reliable programming due to the limitations of electrical fuses and antifuses, which often result in high device resistance or unreliable dielectric breakdown.
Innovation Solution
The development of an OTP memory device incorporating an antifuse structure with a semiconductor-on-insulator (SOI) field effect transistor, where the antifuse dielectric layer is selectively thinned using oxidation or etching processes to create a conductive path upon voltage application, allowing for a controlled and reliable transition between high and low resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical fuses are used for OTP memory programming, then device resistance is reduced upon programming, but the programming reliability is compromised
Solution Approach 1:
The patent changes the resistance parameter behavior by using antifuse structures that increase resistance upon programming rather than reduce it. This is achieved through dielectric breakdown mechanisms that create high-resistance conductive paths, fundamentally altering the resistance parameter from decreasing (fuse) to increasing (antifuse) upon programming event.
Solution Approach 2:
The patent replaces the mechanical/thermal fuse breaking mechanism with an electrical dielectric breakdown mechanism. Instead of physically breaking a conductive path through heat or mechanical stress, the invention uses controlled electrical field-induced dielectric breakdown to create or modify conductive paths, substituting one physical mechanism for another more controllable one.
2Reliability
If antifuse structures are used for OTP memory programming, then programming reliability is improved through controlled dielectric breakdown, but device resistance increases upon programming
Solution Approach 1:
The patent accepts and utilizes the resistance increase parameter change as the desired programming state. By designing the antifuse structure and breakdown characteristics appropriately, the high-resistance state becomes the programmed state, inverting the traditional expectation that programming should reduce resistance.
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between the conductive elements. This dielectric layer acts as the programming element itself - its controlled breakdown serves as the intermediary mechanism that reliably indicates and achieves the programmed state, separating the programming action from the resistance change outcome.
3Manufacturing precision
If existing antifuse structures are used, then increased device resistance is achieved upon programming, but dielectric breakdown reliability is insufficient
Solution Approach 1:
The patent applies local quality by creating spatially varying dielectric layer thicknesses or compositions in different regions of the antifuse structure. This allows different breakdown characteristics in different locations, enabling controlled and reliable breakdown at specific points while maintaining overall structure integrity and predictable resistance increases.
Solution Approach 2:
The patent performs preliminary actions by pre-conditioning the dielectric layer through specific deposition processes, thickness control, or pre-stress applications that prepare the structure for reliable breakdown. The dielectric layer is prepared in advance with specific properties that ensure predictable and reliable breakdown behavior when programming voltage is applied.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed antifuse structure enables a robust and efficient programming mechanism, ensuring reliable dielectric breakdown and reduced device resistance, thereby enhancing the performance and reliability of OTP memory devices.
Implementation Method 1
the antifuse dielectric layer is selectively thinned using oxidation or etching processes to create a conductive path upon voltage application
Implementation Method 2
the antifuse dielectric layer is selectively thinned using oxidation or etching processes to create a conductive path upon voltage application
Implementation Method 3
allowing for a controlled and reliable transition between high and low resistance states
Data Source
AI summary
A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.