Low-Voltage OTP Anti-Fuse Using Damascene Copper Interconnects
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Solution Overview
Problem
Conventional one-time-programmable (OTP) memory devices require high voltage or high current for programming, making them incompatible with standard logic processes and increasing the complexity and cost of integrated circuit fabrication, particularly in CMOS integrated circuits.
Innovation Solution
A semiconductor structure with a stacked configuration including a bottom electrode, a top electrode, and an insulation layer with a breakdown field/voltage lower than the write voltage but higher than the read voltage, using copper metal lines and dielectric layers to form a low-voltage OTP anti-fuse cell compatible with existing CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional OTP memory devices use metal fuses or gate oxide fuses, then programming functionality is achieved, but high voltage or high current is required increasing complexity and cost
Solution Approach 1:
The patent changes the electrical parameters of the insulation layer by selecting materials and thicknesses that provide appropriate breakdown voltages. The insulation layer is designed with specific dielectric properties (breakdown field/voltage) that enable programming at reduced voltages compatible with standard CMOS processes, thus resolving the contradiction between reliable programming and reduced voltage requirements
Solution Approach 2:
The patent employs composite material structures including copper metal lines, various dielectric materials (insulation layer, inter-metal dielectric), and diffusion barrier layers. This composite approach allows optimization of each layer's properties to achieve low-voltage operation while maintaining programming reliability and CMOS compatibility
2Reliability
If conventional OTP memory devices use aluminum interconnect technologies, then OTP functionality is achieved, but compatibility with copper damascene processes is lost
Solution Approach 1:
The patent designs the OTP anti-fuse cell structure to be universally compatible with standard copper damascene interconnect processes. The anti-fuse cell is integrated within the existing copper interconnect layers, allowing the same fabrication process to serve both standard logic functions and OTP programming functions, thus achieving both OTP functionality and process compatibility
Solution Approach 2:
The patent introduces an insulation layer as an intermediary element between the copper interconnect lines. This insulation layer serves as the programming element while being fully compatible with the copper damascene process, acting as a mediator that enables OTP functionality without compromising process compatibility
3Ease of operation
If the insulation layer breakdown voltage is lowered for easier programming, then write voltage is reduced, but read voltage margin is compromised
Solution Approach 1:
The patent applies local quality by creating spatial differentiation in the electrical characteristics of the insulation layer. The insulation layer is designed with specific local properties (breakdown field/voltage) that are optimized for the programming operation, while the overall structure maintains sufficient voltage margins for reliable reading. The breakdown voltage is locally controlled through material selection and thickness optimization to achieve write voltages compatible with CMOS while preserving read voltage margins
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces write voltages and ensures full compatibility with existing integrated circuit formation processes, lowering manufacturing complexity and cost while maintaining functionality.
Implementation Method 1
the insulation layer is configured to be broken down if the write voltage is applied between the top electrode and the bottom electrode
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate, a power source, and a stacked structure over the semiconductor substrate and coupled to the power source. The stacked structure includes a bottom electrode, a top electrode, and an insulation layer between the top electrode and the bottom electrode, wherein the insulation layer has a breakdown voltage lower than a pre-determined write voltage provided by the power source and higher than a pre-determined read voltage provided by the power source.