OTP Bit Formation via Bipolar AC Stress and Power Limiting
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Solution Overview
Problem
Thin film memory devices, such as MRAM, face issues with wide resistance distribution and high breakdown voltage due to the third permanent state created by tunneling barrier breakdown, leading to read failure and circuit complexity, and high power consumption.
Innovation Solution
A method is proposed to form a one-time-programming (OTP) bit using a bipolar alternating current to stress a thin-film memory device, constraining power applied to achieve lower breakdown voltage and tighter resistance distribution, involving a thin-film memory device with a transistor and memory element in series, where the alternating current is applied with a power limiting circuit to irreversibly change the resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tunneling barrier breakdown is used to create OTP state, then permanent third state with lower resistance is achieved, but wide resistance distribution causes read failure and circuit complexity
Solution Approach 1:
The patent changes the electrical parameters applied to the memory device by using alternating current with controlled amplitude and duration, along with transistor gating, to achieve breakdown at lower voltages. This parameter optimization narrows the post-breakdown resistance distribution, reducing read failures and simplifying circuit design while maintaining reliable OTP state formation.
2Reliability
If high breakdown voltage is used for tunneling barrier breakdown, then OTP state is formed, but power consumption increases and select transistor size must be larger
Solution Approach 1:
The patent applies periodic alternating current cycles to the memory device, with each cycle consisting of positive and negative half-cycles. This periodic stress gradually accumulates in the tunneling barrier, enabling breakdown at lower peak voltages compared to single-pulse methods. The transistor is gated during specific cycles to control current flow, further reducing power consumption while achieving reliable OTP programming.
Solution Approach 2:
The patent dynamically controls the transistor gate voltage during the alternating current stress process. By adjusting the transistor's on/off state during different cycles, the current through the memory device is optimized to achieve breakdown at lower voltages. This dynamic control reduces both power consumption and the required transistor size while maintaining programming reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a lower breakdown voltage and tighter distribution of post-breakdown resistances, reducing power consumption and simplifying data reading by narrowing the resistance range, thus improving the reliability and efficiency of the memory device.
Implementation Method 1
Breakdown to the tunneling barrier creates a permanent third state with lower resistance comparing to the two resistance states before barrier breakdown
Implementation Method 2
uses a bipolar current to stress a thin-film memory device and constrains the power applied to the memory device, thereby achieving a lower breakdown voltage
Data Source
AI summary
In a method of forming a one-time-programming (OTP) bit, a thin-film memory device is provided, which includes at least one memory element and a transistor, and the memory element is coupled to the transistor in series. Then, an alternating current is applied to the memory element and the transistor, the power applied to the memory element is constrained, and the transistor is turned on to change the resistance of the memory element for a plurality of cycles of the alternating current until the resistance of the memory element is irreversibly changed.