OTP Bitcell Isolated-Well Layout for High-Voltage Programming
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Solution Overview
Problem
FinFET processes impose layout constraints that prevent the scaling of typical one-time programmable (OTP) anti-fuse bitcells, leading to issues such as source/drain to well diode breakdown and high gate-induced drain leakage, which hinder the programming of anti-fuse bitcells.
Innovation Solution
The formation of OTP bitcells in isolated wells allows for independent well biasing, enabling select devices to withstand programming voltages above diode breakdown and reducing gate-induced drain leakage, thereby facilitating the programming of a large array of bitcells by raising the p-well voltage and reducing voltage on unselected rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If typical OTP anti-fuse bitcells are scaled down using FinFET processes, then device density and integration are improved, but source/drain to well diode breakdown occurs and gate-induced drain leakage increases
Solution Approach 1:
The patent divides the semiconductor substrate into multiple isolated wells, each capable of independent biasing. This segmentation allows the select devices in each well to be independently controlled, enabling the application of different voltages to different wells during programming operations. By isolating the wells, the patent prevents voltage breakdown across well boundaries and reduces gate-induced drain leakage while maintaining high device density through efficient space utilization.
2Area of stationary object
If select devices and anti-fuse core devices share a common diffusion strip, then device area is reduced, but layout rules prevent formation due to thin and thick gate oxide requirements
Solution Approach 1:
The patent implements local quality by forming different well types (first wells and second wells) with different doping types in close proximity. The first wells contain select devices with one gate oxide thickness requirement, while the second wells contain anti-fuse core devices with different gate oxide thickness requirements. This local differentiation allows each region to be optimized for its specific function while maintaining overall compactness, as the wells can be interleaved or adjacent without requiring large separation distances.
3Power
If high programming voltages are applied to anti-fuse bitcells, then programming capability is achieved, but source/drain to well diode breakdown occurs
Solution Approach 1:
The patent introduces isolated wells as intermediary structures between the source/drain regions and the substrate. These wells act as voltage buffers that can be independently biased to prevent breakdown. During programming, the wells containing select devices can be biased to accommodate high programming voltages on the anti-fuse gates without causing source/drain to well diode breakdown, as the well biasing creates a voltage gradient that protects the diode junctions.
4Area of stationary object
If device scaling is pursued to increase density, then footprint is reduced, but gate-induced drain leakage increases significantly
Solution Approach 1:
The patent implements dynamic biasing of the isolated wells, where the well voltages can be adjusted based on the operational state. During programming operations, specific wells can be biased to minimize gate-induced drain leakage in adjacent devices. The ability to dynamically change well voltages allows the system to adapt to different operational requirements, reducing leakage currents while maintaining compact device scaling.
Data Source
AI summary
A semiconductor memory includes, in part, M×N select transistors disposed along M rows and N columns, where M and N are integers greater than or equal to 2. The memory further includes, in part, a first set of M wells each configured to be biased independently of the remaining M−1 wells. Each well has formed therein N of the select transistors each having a source/drain terminal coupled to the same bitline corresponding to a different one of M bitlines of the memory. The memory further includes, in part, M×N anti-fuses. Each anti-fuse is associated and forms a bitcell with a corresponding one of the M×N select transistors.