OTP Bitcell Select Device with Local Doping to Reduce GIDL
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
One-time programmable (OTP) memory devices in IoT applications face significant gate-induced drain leakage (GIDL) due to high inhibit voltages applied to unselected bitcells, which increases power consumption and can lead to latent gate oxide damage, especially in low power supply voltage processes.
Innovation Solution
The OTP memory device incorporates a select device with a drain formed in a low doped region and a portion of the select device positioned above this region, reducing GIDL without requiring high current supply or increasing device size, by utilizing a low doped region under the drain and a higher doped region for the select device, thereby minimizing tunneling leakage across the p-n junction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high inhibit voltage (e.g., 2.9V) is applied to the drain of unselected bitcells to prevent accidental programming, then programming reliability is improved, but gate-induced drain leakage (GIDL) increases causing excessive power consumption
Solution Approach 1:
The patent applies different doping concentrations to different regions: a low-doped region under the drain to minimize GIDL, and a higher-doped region for the select device channel to maintain proper transistor operation. This local differentiation allows the drain to tolerate high inhibit voltages with minimal leakage while the select device remains functional.
2Reliability
If a high inhibit voltage is applied to unselected bitcells, then programming reliability is improved, but latent gate oxide damage occurs reducing device lifetime
Solution Approach 1:
The low-doped region is specifically positioned under the drain where the high electric field during inhibit operations occurs. This localized low-doping structure reduces the peak electric field strength at the drain edge, minimizing tunneling into the gate oxide and preventing latent damage that would reduce device lifetime.
3Use of energy by moving object
If the doping concentration under the drain is increased to reduce GIDL, then power consumption is reduced, but the select device performance deteriorates
Solution Approach 1:
The patent uses a higher-doped region specifically for the select device channel formation area to ensure proper transistor threshold voltage and on-current characteristics. The low-doped region is confined to the drain area only, creating a spatial separation of doping profiles that simultaneously optimizes both power consumption and device performance.
Solution Approach 2:
The substrate is segmented into distinct doped regions: a low-doped region under the drain for minimizing GIDL, and a higher-doped region for the select device channel. This segmentation allows each region to be optimized independently for its specific function without compromising the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces GIDL, minimizing power consumption and preventing latent gate oxide damage, while maintaining reliable programming and read operations in IoT devices with low power supply voltages.
Implementation Method 1
minimizing tunneling leakage across the p-n junction
Data Source
AI summary
An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A drain region and a source region of an opposite polarity are also in the semiconductor substrate. The drain region is positioned over the first, higher doped region, and the drain is positioned over the second, lower doped region. The select device above the semiconductor substrate can form a channel in a channel region of the semiconductor substrate between the source region and the drain region. One portion of the select device is positioned over the first, lower doped region, and another portion of the select device is positioned over the second, higher doped region. An anti-fuse device is positioned above the second doped region and in part above a portion of the source region.